MC908GR16ACFAE Freescale Semiconductor, MC908GR16ACFAE Datasheet - Page 143

IC MCU 16K FLASH 8MHZ 48-LQFP

MC908GR16ACFAE

Manufacturer Part Number
MC908GR16ACFAE
Description
IC MCU 16K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908GR16ACFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Chapter 14
Enhanced Serial Communications Interface (ESCI) Module
14.1 Introduction
The enhanced serial communications interface (ESCI) module allows asynchronous communications
with peripheral devices and other microcontroller units (MCU).
14.2 Features
Features include:
14.3 Pin Name Conventions
The generic names of the ESCI input/output (I/O) pins are:
ESCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an ESCI input or output
reflects the name of the shared port pin.
ESCI I/O pins. The generic pin names appear in the text of this section.
Freescale Semiconductor
Full-duplex operation
Standard mark/space non-return-to-zero (NRZ) format
Programmable baud rates
Programmable 8-bit or 9-bit character length
Separately enabled transmitter and receiver
Separate receiver and transmitter central processor unit (CPU) interrupt requests
Programmable transmitter output polarity
Two receiver wakeup methods:
Interrupt-driven operation with eight interrupt flags:
Receiver framing error detection
Hardware parity checking
1/16 bit-time noise detection
RxD (receive data)
TxD (transmit data)
Idle line wakeup
Address mark wakeup
Transmitter empty
Transmission complete
Receiver full
Idle receiver input
Receiver overrun
Noise error
Framing error
Parity error
MC68HC908GR16A Data Sheet, Rev. 1.0
Table 14-1
shows the full names and the generic names of the
143

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