MC908GR16ACFAE Freescale Semiconductor, MC908GR16ACFAE Datasheet - Page 68

• Manufacturer Part Number: MC908GR16ACFAE
• Description: IC MCU 16K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR16ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Clock Generator Module (CGM)
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
4.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
AUTO — Automatic Bandwidth Control Bit
68
These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction
with L controls the hardware center-of-range frequency, f
PLLON bit is set. Reset clears these bits. (See
4.5.5 PLL VCO Range Select
•
•
•
•
This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual
operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
Selects automatic or manual (software-controlled) bandwidth control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking mode
Address:
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMVCLK requires two writes to the PLL control register. (See
4.3.8 Base Clock Selector
Verify that the value of the VPR1 and VPR0 bits in the PCTL register are
appropriate for the given reference and VCO clock frequencies before
enabling the PLL. See
on selecting the proper value for these control bits.
Reset:
Read:
Write:
1. Do not program E to a value of 3.
$0037
AUTO
Bit 7
Figure 4-5. PLL Bandwidth Control Register (PBWC)
0
VPR1 and VPR0
Table 4-4. VPR1 and VPR0 Programming
= Unimplemented
00
01
10
LOCK
Register.)
6
0
MC68HC908GR16A Data Sheet, Rev. 1.0
4.3.6 Programming the PLL
ACQ
Circuit.).
5
0
2
NOTE
E
0
1
(1)
4.3.3 PLL
R
4
0
0
= Reserved
VRS
3
0
0
Circuits,
VCO Power-of-Two
Range Multiplier
. VPR1:VPR0 cannot be written when the
for detailed instructions
1
2
4
4.3.6 Programming the
2
0
0
1
0
0
Freescale Semiconductor
Bit 0
R
0
PLL, and