MC908GR16ACFAE Freescale Semiconductor, MC908GR16ACFAE Datasheet - Page 205

• Manufacturer Part Number: MC908GR16ACFAE
• Description: IC MCU 16K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR16ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

To protect status bits during the break state, write a 0 to BCFE. With BCFE at 0 (its default state), software
can read and write I/O registers during the break state without affecting status bits. Some status bits have
a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the
bit cannot change during the break state as long as BCFE is 0. After the break, doing the second step
clears the status bit.
Since the SPTE bit cannot be cleared during a break with BCFE cleared, a write to the transmit data
register in break mode does not initiate a transmission nor is this data transferred into the shift register.
Therefore, a write to the SPDR in break mode with BCFE cleared has no effect.
16.11 I/O Signals
The SPI module has four I/O pins:
The SPI has limited inter-integrated circuit (I
single-master environment. To communicate with I
when the SPWOM bit in the SPI control register is set. In I
are connected to a bidirectional pin from the I
16.11.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin
of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI
simultaneously receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is
configured as a slave when its SPMSTR bit is 0 and its SS pin is low. To support a multiple-slave system,
a high on the SS pin puts the MISO pin in a high-impedance state.
When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction
register of the shared I/O port.
16.11.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmits serial data. In full-duplex operation, the MOSI pin
of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI
simultaneously transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction
register of the shared I/O port.
16.11.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master MCU,
the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex
operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
Freescale Semiconductor
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MISO — Master input/slave output
MOSI — Master output/slave input
SPSCK — Serial clock
SS — Slave select
MC68HC908GR16A Data Sheet, Rev. 1.0
2
C) capability (requiring software support) as a master in a
2
C peripheral and through a pullup resistor to V
2
C peripherals, MOSI becomes an open-drain output
2
C communication, the MOSI and MISO pins
DD
I/O Signals
.
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