MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 109

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908LD64
Freescale Semiconductor
NOTE:
NOTE:
—
Rev. 3.0
MUL[7:4] — Multiplier Select Bits
The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
VRS[7:4] — VCO Range Select Bits
The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming may result in failure of the PLL to achieve lock.
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. A value of $0 in the multiplier select
bits configures the modulo feedback divider the same as a value of
$1. Reset initializes these bits to $6 to give a default multiply value
of 6.
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency
f
control register (PCTL) is set. A value of $0 in the VCO range select
bits disables the PLL and clears the BCS bit in the PCTL. Reset
initializes the bits to $6 to give a default range multiply value of 6.
VRS
MUL7:MUL6:MUL5:MUL4
. VRS[7:4] cannot be written when the PLLON bit in the PLL
Table 8-2. VCO Frequency Multiplier (N) Selection
Clock Generator Module (CGM)
0000
0001
0010
0011
1101
1110
1111
VCO Frequency Multiplier (N)
Clock Generator Module (CGM)
13
14
15
1
1
2
3
CGM I/O Registers
Data Sheet
109