MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 194

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Module (USB)
14.6 Hub Function I/O Registers
14.6.1 USB Hub Root Port Control Register (HRPCR)
Data Sheet
194
Address:
The USB hub function provides a set of control/status registers and
sixteen data registers that provide storage for the buffering of data
between the USB hub function and the CPU.
RESUM0 — Force Resume to the Root Port
SUSPND — USB Suspend Control Bit
Reset:
Read:
Write:
This read/write bit forces a resume signal (K state) onto the USB root
port data lines to initiate a remote wakeup. Software should control
the timing of the forced resume to be between 10ms and 15ms.
Reset clears this bit.
To save power, this read/write bit should be set by the software if a
constant idle state for more than 3ms is detected on the USB bus.
Setting this bit puts the transceiver into a power savings mode.
This bit also determines the latch scheme for the data lines of the root
port and the downstream port. When this bit is 1, the current state
shown on the data lines will be reflected to the data register (D+/D–)
directly. When the bit is 0, the data registers are the latched state
sampled at the last EOF2 sample point. The hub repeater’s function
is affected by this bit too. The upstream and downstream traffic will be
blocked if this bit is set to 1. When the global resume or the
downstream remote wakeup signal is found by the suspended hub,
Figure 14-3. USB Hub Root Port Control Register (HRPCR)
1 = Force root port data lines to K state
0 = Default
X = Indeterminate
$005E
Bit 7
Universal Serial Bus Module (USB)
0
0
6
0
0
5
0
0
RESUM0 SUSPND
= Unimplemented
4
0
3
0
MC68HC908LD64
Freescale Semiconductor
2
0
0
D0+
X
1
—
Rev. 3.0
Bit 0
D0–
X