MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 117

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.3 SIM Bus Clock Control and Generation
9.3.1 Bus Timing
9.3.2 Clock Start-Up from POR
9.3.3 Clocks in Stop Mode and Wait Mode
MC68HC908LD64
Freescale Semiconductor
From
SIM
SIMOSCEN
—
Rev. 3.0
OSC1
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in
In user mode, the internal bus frequency is the oscillator frequency
(OSCXCLK) divided by four.
When the power-on reset module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after
the 4096 OSCXCLK cycle POR timeout has completed. The RST is
driven low by the SIM during this entire period. The IBUS clocks start
upon completion of the timeout.
Upon exit from stop mode (by an interrupt, break, or reset), the SIM
allows OSCXCLK to clock the SIM counter. The CPU and peripheral
clocks do not become active until after the stop delay timeout. This
timeout is selectable as 4096 or 32 OSCXCLK cycles. (See
Mode.)
Figure 9-3. OSC Clock Signals
System Integration Module (SIM)
OSC2
OSCILLATOR
÷ 2
OSCXCLK
OSCOUT
SIM Bus Clock Control and Generation
Figure
System Integration Module (SIM)
÷ 2
SIM COUNTER
9-3.
SIM
GENERATORS
BUS CLOCK
9.7.2 Stop
Data Sheet
117