MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 76

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Configuration Register (CONFIG)
5.4 Configuration Register
Data Sheet
76
NOTE:
Address:
Reset:
SSREC — Short Stop Recovery Bit
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Bit
STOP — STOP Instruction Enable Bit
COPD — COP Disable Bit
Read:
Write:
SSREC enables the CPU to exit stop mode with a delay of 32
OSCXCLK cycles instead of a 4096 OSCXCLK cycle delay.
COPRS selects the COP timeout period. Reset clears COPRS. (See
Section 22. Computer Operating Properly
STOP enables the STOP instruction.
COPD disables the COP module. (See
Operating Properly
1 = Stop mode recovery after 32 OSCXCLK cycles
0 = Stop mode recovery after 4096 OSCXCLK cycles
1 = COP timeout period = 2
0 = COP timeout period = 2
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
$001F
Bit 7
0
0
Configuration Register (CONFIG)
Figure 5-1. Configuration Register (CONFIG)
= Unimplemented
6
0
0
(COP).)
5
0
0
13
18
4
0
0
– 2
– 2
4
4
SSREC
OSCXCLK cycles
OSCXCLK cycles
3
0
Section 22. Computer
MC68HC908LD64
COPRS
(COP).)
Freescale Semiconductor
2
0
STOP
1
0
—
Rev. 3.0
COPD
Bit 0
0