M37542F8FP#U0 Renesas Electronics America, M37542F8FP#U0 Datasheet - Page 120

• Manufacturer Part Number: M37542F8FP#U0
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
1.00 Nov 27, 2002
2.00 Apr 21, 2003
2.01 Dec 03, 2003
2.02 Jan 06, 2004
Date
REVISION HISTORY
85 to103
65 to 72
73 to 82
Page
10
28
36
37
53
55
56
57
13
15
28
30
33
34
40
51
54
59
64
65
68
69
70
71
10
79
82
83
84
91
93
1
8
9
1
8
9
1
–
First edition issued
FEATURES; Memory size revised.
Memory size; Flash memory size revised.
Fig.8; ROM size revised.
Table 2; ROM size revised.
Central Processing Unit (CPU); Description revised.
Fig.26; Port P0
Fig.42; Modulation output revised.
Fig.43; Modulation output revised.
Reset Circuit; Description revised.
(3) RC oscillation; Description revised.
(1) Oscillation control
• Stop mode
Description about FLASH added.
Fig.77; revised.
FLASH MEMORY MODE added.
ELECTRICAL CHARACTERISTICS added.
FEATURES: Interrupt, Power source voltage, Power dissipation revised.
Fig. 8: Development schedule revised.
Table 2: ROM size for Flash memory version revised.
Fig. 12: Note added.
Fig. 14: Flash memory control register 2 added.
Fig. 26: “CPU mode register” added, description for timer 1 interrupt request revised.
Fig. 29: “CPU mode register” added.
Fig. 37 and Fig. 38: Pin name added.
Fig. 39: Pin name added.
Fig. 46 and Fig. 47: Pin name added.
A-D Converter revised.
Fig. 70 Flash memory control register 2 added.
Fig. 79 (5), (6) revised.
DATA REQUIRED FOR MASK ORDERS revised.
Description of flash memory control register 0 (bit 2), Fig. 83 revised.
Description of flash memory control register 2, Fig. 85 and Table 8 added.
Fig. 86 revised.
Table 9 revised.
ELECTRICAL CHARACTERISTICS;
General purpose revised.
Extended operating temperature version added.
FEATURES: The minimum instruction execution time revised.
Note 2 eliminated.
Stack pointer (S): Reference number of Figure in description revised.
Table 12: P0
Fig. 95: “BUSY” added to P0
Fig. 96, Fig. 97: “BUSY” added to P0
Fig. 98, Fig. 99: CNV
Table 19, Table 20 Timing requirements (General purpose)
Vcc for FLASH ROM version and Mask ROM version revised.
Table 22, Table 23 Switching characteristics (General purpose)
Vcc for FLASH ROM version and Mask ROM version revised.
A-D Converter revised.
7
(BUSY output) added.
3
direction register revised.
SS
A - 1
revised.
7
Description
.
Summary
7542 Group Datasheet
7
.