M37542F8FP#U0 Renesas Electronics America, M37542F8FP#U0 Datasheet - Page 53

• Manufacturer Part Number: M37542F8FP#U0
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Fig. 62 Timing diagram of bus collision detection interrupt
7542 Group
Bus collision detection (SIO1)
SIO1 can detect a bus collision by setting UART1 bus collision de-
tection interrupt enable bit.
When transmission is started in the clock synchronous or asyn-
chronous (UART) serial I/O mode, the transmit pin TxD
compared with the receive pin RxD
edge of transmit shift clock. If they do not coincide with each other,
a bus collision detection interrupt request occurs.
When a transmit data collision is detected between LSB and MSB
of transmit data in the clock synchronous serial I/O mode or be-
tween the start bit and stop bit of transmit data in UART mode, a
bus collision detection can be performed by both the internal clock
and the external clock.
A block diagram is shown in Fig. 61.
A timing diagram is shown in Fig. 62.
Note: Bus collision detection can be used when SIO1 is operating
Fig. 61 Block diagram of bus collision detection interrupt circuit
Rev.3.03
REJ03B0006-0303
at full-duplex communication. When SIO1 is operating at
half-duplex communication, set bus collision detection inter-
rupt to be disabled.
Jul 11, 2008
UART1 bus collision detection
Transmit shift clock
TxD
RxD
Shift clock
Transmit pin TxD
Receive pin RxD
Page 51 of 117
1
1
(Address 000A
1
in synchronization with rising
interrupt valid bit
1
1
16
, bit 1)
D
1
is
Q
Key-on wakeup interrupt request
Fig. 60 Bus collision detection circuit related registers
b7
b7
b7
b7
UART1 bus collision detection
interrupt discrimination bit
(Address 000B
Data collision
Key-on wakeup/
UART1 bus collision detection
interrupt request bit
(Address 003C
16
, bit 1)
b0
b0
b0
b0
Interrupt source set register
Interrupt source discrimination register
Interrupt request register 1
(IREQ1 : address 003C
Interrupt control register 1
(ICON1 : address 003E
(INTSET: address 000A
(INTDIS: address 000B
Bus collision detection
interrupt generation
Key-on wakeup interrupt valid bit
UART1 bus collision detection
interrupt valid bit
A/D conversion interrupt valid bit
Timer 1 interrupt valid bit
Not used (returns “0” when read)
Key-on wakeup interrupt discrimination bit
discrimination bit
A/D conversion interrupt discrimination bit
Timer 1 interrupt discrimination bit
Not used (returns “0” when read)
Serial I/O1 receive interrupt request bit
INT
INT
Key-on wake up/UART1 bus collision
detection interrupt request bit
CNTR
Serial I/O1 receive interrupt enable bit
INT
INT
Key-on wake up/UART1 bus collision
detection interrupt enable bit
CNTR
UART1 bus collision detection interrupt
Serial I/O1 transmit interrupt request bit
Serial I/O2 receive interrupt request bit
Serial I/O2 transmit interrupt request bit
Serial I/O1 transmit interrupt enable bit
Serial I/O2 receive interrupt enable bit
Serial I/O2 transmit interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
1 : Interrupt request issued
0 : No interrupt request issued
16
0: Interrupt does not occur
1: Interrupt occurs
0: Interrupt invalid
1: Interrupt valid
0
1
0
1
, bit 6)
interrupt request bit
interrupt request bit
interrupt enable bit
interrupt enable bit
0
0
interrupt request bit
interrupt enable bit
16
16
16
16
, initial value : 00
, initial value: 00
, initial value : 00
, initial value: 00
16
16
16
16
)
)
)
)