M37542F8FP#U0 Renesas Electronics America, M37542F8FP#U0 Datasheet - Page 27

• Manufacturer Part Number: M37542F8FP#U0
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes1: Vector addresses contain internal jump destination addresses.
7542 Group
Interrupts
The 7542 Group interrupts are vector interrupts with a fixed prior-
ity scheme, and generated by 16 sources among 18 sources: 6
external, 11 internal, and 1 software.
The interrupt sources, vector addresses
are shown in Table 8.
Each interrupt except the BRK instruction interrupt has the inter-
rupt request bit and the interrupt enable bit. These bits and the
interrupt disable flag (I flag) control the acceptance of interrupt re-
quests. Figure 23 shows an interrupt control diagram.
Table 8 Interrupt vector addresses and priority
Rev.3.03
REJ03B0006-0303
Reset (Note 2)
Serial I/O1 receive
Serial I/O1 transmit
Serial I/O2 receive
Serial I/O2 transmit
INT
INT
Key-on wake-up/
UART1 bus
collision detection
(Note 3)
CNTR
Capture 0
Capture 1
Compare
Timer X
Timer A
Timer B
A/D conversion/
Timer 1 (Note 4)
BRK instruction
Interrupt source
0
1
2: Reset function in the same way as an interrupt with the highest priority.
3: Key-on wakeup interrupt and UART1 bus collision detection interrupt can be enabled by setting of interrupt source set register. The occurrence of
4: A/D conversion interrupt and Timer 1 interrupt can be enabled by setting of interrupt source set register. The occurrence of these interrupts are dis-
0
these interrupts are discriminated by interrupt source discrimination register.
criminated by interrupt source discrimination register.
Jul 11, 2008
Priority
10
12
13
14
15
16
17
11
1
2
3
4
5
6
7
8
9
Vector addresses (Note 1)
High-order
FFFD
FFED
FFEB
FFDF
FFDD
FFFB
FFEF
FFE9
FFE7
FFE5
FFE3
FFF9
FFF7
FFF5
FFF3
FFF1
FFE1
Page 25 of 117
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
(1)
Low-order
FFFC
FFEE
FFEC
FFEA
FFDE
FFDC
, and interrupt priority
FFFA
FFE8
FFE6
FFE4
FFE2
FFE0
FFF8
FFF6
FFF4
FFF2
FFF0
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
At reset input
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit shift
or when transmit buffer is empty
At completion of serial I/O2 data receive
At completion of serial I/O2 transmit shift
or when transmit buffer is empty
At detection of either rising or falling edge
of INT
At detection of either rising or falling edge
of INT
At falling of conjunction of input logical
level for port P0 (at input)
At detection of UART1 bus collision
detection
At detection of either rising or falling edge
of CNTR
At detection of either rising or falling edge
of Capture 0 input
At detection of either rising or falling edge
of Capture 1 input
At compare matched
At timer X underflow
At timer A underflow
At timer B underflow
At completion of A/D conversion
At timer 1 underflow
At BRK instruction execution
Interrupt request generating conditions
0
1
input
input
0
input
An interrupt request is accepted when all of the following condi-
tions are satisfied:
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
• Interrupt disable flag.................................“0”
• Interrupt request bit...................................“1”
• Interrupt enable bit....................................“1”
Non-maskable
Valid only when serial I/O1 is selected
Valid only when serial I/O1 is selected
Valid only when serial I/O2 is selected
Valid only when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(valid at falling edge)
When UART1 bus collision detection
interrupt is enabled.
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Compare interrupt source is selected.
STP release timer underflow
Non-maskable software interrupt
Remarks