MC9S12GC96MFAE Freescale Semiconductor, MC9S12GC96MFAE Datasheet - Page 169
![IC MCU 96K FLASH 25MHZ 48-LQFP](/photos/12/19/121954/mc9s12gc96mfae_sml.jpg)
MC9S12GC96MFAE
Manufacturer Part Number
MC9S12GC96MFAE
Description
IC MCU 96K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12GC16MFUE.pdf
(690 pages)
Specifications of MC9S12GC96MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12GC
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE, M68DKIT912C32SLK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12GC96MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12GC96MFAE
Manufacturer:
FRE/MOT
Quantity:
20 000
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6.3.2
Freescale Semiconductor
BDMCCR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BDMSTS
Register
BDMINR
0xFF0A
0xFF0B
0xFF00
0xFF01
0xFF02
0xFF03
0xFF04
0xFF05
0xFF06
0xFF07
0xFF08
0xFF09
Name
Register Descriptions
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
ENBDM
CCR7
Bit 7
X
X
X
X
X
X
X
X
0
0
0
= Unimplemented, Reserved
= Indeterminate
BDMACT
REG14
CCR6
X
X
X
X
X
X
X
6
0
0
Figure 6-2. BDM Register Summary
MC9S12C-Family / MC9S12GC-Family
ENTAG
REG13
CCR5
X
X
X
X
X
X
X
5
0
0
Rev 01.24
Chapter 6 Background Debug Module (BDMV4) Block Description
REG12
CCR4
SDV
X
X
X
X
X
X
X
4
0
0
TRACE
REG11
CCR3
X
X
X
X
X
X
X
3
0
0
0
= Implemented (do not alter)
= Always read zero
CLKSW
CCR2
2
X
X
X
X
X
0
0
0
X
X
UNSEC
CCR1
1
0
X
X
X
X
0
0
0
X
X
CCR0
Bit 0
X
X
X
X
X
X
0
0
0
0
0
169
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