MC9S12GC96MFAE Freescale Semiconductor, MC9S12GC96MFAE Datasheet - Page 418
![IC MCU 96K FLASH 25MHZ 48-LQFP](/photos/12/19/121954/mc9s12gc96mfae_sml.jpg)
MC9S12GC96MFAE
Manufacturer Part Number
MC9S12GC96MFAE
Description
IC MCU 96K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12GC16MFUE.pdf
(690 pages)
Specifications of MC9S12GC96MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12GC
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE, M68DKIT912C32SLK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12GC96MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12GC96MFAE
Manufacturer:
FRE/MOT
Quantity:
20 000
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Chapter 14 Serial Peripheral Interface (SPIV3) Block Description
14.3.2.2
Read: anytime
Write: anytime; writes to the reserved bits have no effect
418
Module Base 0x0001
MODFEN
BIDIROE
SPISWAI
Reset
SPC0
Field
4
3
1
0
W
R
Bidirectional
Pin Mode
Normal
Normal
Mode Fault Enable Bit — This bit allows the MODF failure being detected. If the SPI is in master mode and
MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an
input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin
configuration refer to
force the SPI system into idle state.
0 SS port pin is not used by the SPI
1 SS port pin with MODF feature
Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer
of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode this bit controls the output
buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0
set, a change of this bit will abort a transmission in progress and force the SPI into idle state.
0 Output buffer disabled
1 Output buffer enabled
SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
0 SPI clock operates normally in wait mode
1 Stop SPI clock generation when in wait mode
Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in
mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state
SPI Control Register 2 (SPICR2)
0
0
7
= Unimplemented or Reserved
0
0
6
SPC0
0
1
0
Table
Figure 14-4. SPI Control Register 2 (SPICR2)
Table 14-5. Bidirectional Pin Configurations
Table 14-4. SPICR2 Field Descriptions
14-3. In master mode, a change of this bit will abort a transmission in progress and
MC9S12C-Family / MC9S12GC-Family
BIDIROE
0
0
5
X
0
1
X
Master Mode of Operation
Slave Mode of Operation
MODFEN
Rev 01.24
MISO not used by SPI
0
4
Description
Slave Out
Master In
MISO
BIDIROE
0
3
0
0
2
Master Out
Master I/O
Master In
Slave In
MOSI
SPISWAI
Freescale Semiconductor
Table
0
1
14-5. In master
SPC0
0
0
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