MC9S12GC96MFAE Freescale Semiconductor, MC9S12GC96MFAE Datasheet - Page 294
![IC MCU 96K FLASH 25MHZ 48-LQFP](/photos/12/19/121954/mc9s12gc96mfae_sml.jpg)
MC9S12GC96MFAE
Manufacturer Part Number
MC9S12GC96MFAE
Description
IC MCU 96K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12GC16MFUE.pdf
(690 pages)
Specifications of MC9S12GC96MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12GC
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE, M68DKIT912C32SLK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12GC96MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12GC96MFAE
Manufacturer:
FRE/MOT
Quantity:
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
1. The MSCAN must be in normal mode for this bit to become set.
2. See the Bosch CAN 2.0A/B specification for a detailed definition of transmitter and receiver states.
3. In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when
4. The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see
5. The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1).
6. The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1).
7. In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when
8. Not including WUPE, INITRQ, and SLPRQ.
9. TSTAT1 and TSTAT0 are not affected by initialization mode.
10. RSTAT1 and RSTAT0 are not affected by initialization mode.
10.3.2.2
The CANCTL1 register provides various control bits and handshake status information of the MSCAN
module as described below.
294
INITRQ
SLPRQ
the CPU enters wait (CSWAI = 1) or stop mode (see
“Operation in Stop
“MSCAN Receiver Interrupt Enable Register
the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode
(SLPRQ = 1 and SLPAK = 1) before requesting initialization mode.
Field
1
0
(6),(7)
(5)
Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving
mode (see
idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry
to sleep mode by setting SLPAK = 1 (see
cannot be set while the WUPIF flag is set (see
Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN
detects activity on the CAN bus and clears SLPRQ itself.
0 Running — The MSCAN functions normally
1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle
Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see
Section 10.4.5.5, “MSCAN Initialization
synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1
(Section 10.3.2.2, “MSCAN Control Register 1
The following registers enter their hard reset state and restore their default values: CANCTL0
CANRIER
The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be
written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the
error counters are not affected by initialization mode.
When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the
MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN
is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits.
Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after
initialization mode is exited, which is INITRQ = 0 and INITAK = 0.
0 Normal operation
1 MSCAN in initialization mode
MSCAN Control Register 1 (CANCTL1)
Mode”)
(10)
Section 10.4.5.4, “MSCAN Sleep
Table 10-1. CANCTL0 Register Field Descriptions (continued)
, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL.
.
MC9S12C-Family / MC9S12GC-Family
(CANRIER)) is enabled, if the recovery mechanism from stop or wait is required.
Mode”). Any ongoing transmission or reception is aborted and
Section 10.4.5.2, “Operation in Wait
Section 10.3.2.2, “MSCAN Control Register 1
Rev 01.24
Mode”). The sleep mode request is serviced when the CAN bus is
Section 10.3.2.5, “MSCAN Receiver Flag Register
(CANCTL1)”).
Description
Mode” and
Freescale Semiconductor
(CANCTL1)”). SLPRQ
Section 10.4.5.3,
(8)
Section 10.3.2.6,
, CANRFLG
(CANRFLG)”).
(9)
,
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