MC9S12GC96MFAE Freescale Semiconductor, MC9S12GC96MFAE Datasheet - Page 60
![IC MCU 96K FLASH 25MHZ 48-LQFP](/photos/12/19/121954/mc9s12gc96mfae_sml.jpg)
MC9S12GC96MFAE
Manufacturer Part Number
MC9S12GC96MFAE
Description
IC MCU 96K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12GC16MFUE.pdf
(690 pages)
Specifications of MC9S12GC96MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12GC
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE, M68DKIT912C32SLK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12GC96MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12GC96MFAE
Manufacturer:
FRE/MOT
Quantity:
20 000
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.5.3.3
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and data bus) will be fully static. All peripherals stay
active. For further power consumption reduction the peripherals can individually turn off their local clocks.
1.5.3.4
Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save
power.
1.6
Consult the Exception Processing section of the CPU12 Reference Manual for information.
1.6.1
Table 1-9
60
$FFEE, $FFEF
$FFEC, $FFED
0xFFEC, 0xFFED
0xFFFC, 0xFFFD
0xFFEE, 0xFFEF
0xFFEA, 0xFFEB
0xFFFE, 0xFFFF
0xFFFA, 0xFFFB
0xFFE8, 0xFFE9
0xFFE6, 0xFFE7
0xFFE4, 0xFFE5
0xFFE2, 0xFFE3
0xFFE0, 0xFFE1
Vector Address
0xFFF8, 0xFFF9
0xFFF6, 0xFFF7
0xFFF4, 0xFFF5
0xFFF2, 0xFFF3
0xFFF0, 0xFFF1
Resets and Interrupts
lists interrupt sources and vectors in default order of priority.
Vectors
Wait
Run
(see CRG flags register to determine
Unimplemented instruction trap
External reset, power on reset,
Standard timer channel 0
Standard timer channel 1
Standard timer channel 2
Standard timer channel 3
Standard timer channel 4
Standard timer channel 5
Standard timer channel 6
Standard timer channel 7
Clock monitor fail reset
or low voltage reset
Real time Interrupt
Interrupt Source
COP failure reset
reset source)
Table 1-9. Interrupt Vector Locations
XIRQ
SWI
IRQ
MC9S12C-Family / MC9S12GC-Family
Rev 01.24
Mask
None
None
None
None
None
CCR
X-Bit
Reserved
Reserved
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
COPCTL (CME, FCME)
INTCR (IRQEN)
COP rate select
CRGINT (RTIE)
Local Enable
TIE (C0I)
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
None
None
None
None
Freescale Semiconductor
HPRIO Value
to Elevate
0x00EE
0x00EC
0x00EA
0x00F2
0x00F0
0x00E8
0x00E6
0x00E4
0x00E2
0x00E0
—
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