HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 18

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 CPU
Data Structure in Memory: Figure 1-2 shows the structure of data in memory. The H8/300L
CPU is able to access word data in memory (MOV.W instruction), but only if the word data starts
from an even-numbered address. If an odd address is designated, no address error occurs, but the
access is performed starting from the previous even address, with the least significant bit of the
address regarded as 0.* The same applies to instruction codes.
*
The stack is always accessed a word at a time. When the CCR is pushed on the stack, two identical
copies of the CCR are pushed to make a complete word. When they are returned, the lower byte is
ignored.
Rev. 2.00 Dec 27, 2004 page 4 of 128
REJ09B0214-0200
1-Bit data
CCR: Condition code register.
Note: Word data must begin at an even address.
*
Byte data
Word data
Byte data (CCR) on stack
Word data on stack
:
Note that the LSIs in the H8/300L Series also contain on-chip peripheral modules for
which access in word size is not possible. Details are given in the applicable hardware
manual.
Ignored when returned.
Data type
Figure 1-2 Memory Data Formats
Address
Address n
Address n
Even address
Even address
Even address
Odd address
Odd address
Odd address
7 6 5 4 3 2 1 0
7
M
S
B
M
S
B
M
S
B
M
S
B
M
S
B
Data format
Upper 8 bits
Upper 8 bits
Lower 8 bits
Lower 8 bits
CCR
CCR
*
0
L
S
B
L
S
B
L
S
B
L
S
B
L
S
B