HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 46

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 Instruction Set
The parts of the table are explained below.
Name: The full and mnemonic names of the instruction are given at the top of the page.
Operation: The instruction is described in symbolic notation. The following symbols are used.
* General registers are either 8 bits (R0H/R0L - R7H/R7L) or 16 bits (R0 - R7).
Assembly-Language Format:
The assembly-language coding
of the instruction is given. An
example is:
Rev. 2.00 Dec 27, 2004 page 32 of 128
REJ09B0214-0200
Symbol
Rd
Rs
Rn
<EAd>
<EAs>
PC
SP
CCR
N
Z
V
C
disp
+
–
¬
( ) < >
Meaning
General register (destination)*
General register (source)*
General register*
Destination operand
Source operand
Program counter
Stack pointer
Condition code register
N (negative) flag of CCR
Z (zero) flag of CCR
V (overflow) flag of CCR
C (carry) flag of CCR
Displacement
Transfer from left operand to right operand; or state transition
from left state to right state.
Addition
Subtraction
Multiplication
Division
AND logical
OR logical
Exclusive OR logical
Inverse logic (logical complement)
Contents of operand effective address
Mnemonic Size Source Destination
ADD. B
<EAs>, Rd