PIC18LF2431-I/SP Microchip Technology, PIC18LF2431-I/SP Datasheet - Page 157

IC MCU FLASH 8KX16 28-DIP

PIC18LF2431-I/SP

Manufacturer Part Number
PIC18LF2431-I/SP
Description
IC MCU FLASH 8KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF2431-I/SP

Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
24
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
24
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
17.1.2
The Period Measurement mode is selected by setting
CAPxM<3:0> = 0101. In this mode, the value of Timer5
is latched into the CAPxBUF register on the rising edge
of the input capture trigger and Timer5 is subsequently
reset to 0000h (optional by setting CAPxREN = 1) on
the next T
Figure
17.1.3
The Pulse-Width Measurement mode can be configured
for two different edge sequences, such that the pulse
width is based on either the falling to rising edge of the
CAPx input pin (CAPxM<3:0> = 0110), or on the rising
to falling edge (CAPxM<3:0> = 0111).
FIGURE 17-5:
 2010 Microchip Technology Inc.
Note 1: TMR5 is a synchronous time base input to the input capture; prescaler = 1:1. It increments on every Q1 rising edge.
TMR5
CAP1 Pin
CAP1BUF
TMR5 Reset
Instruction
Execution
17-4).
2: IC1 is configured in Pulse-Width Measurement mode (CAP1M<3:0> = 0111, rising to falling pulse-width
3: TMR5 value is latched by CAP1BUF on T
4: TMR5 Reset is normally an asynchronous Reset signal to TMR5. When used in Pulse-Width Measurement mode, it
5: TMR5 Reset pulse is activated on the capture edge. The CAP1REN bit has no bearing in this mode.
(1)
CY
(2)
PERIOD MEASUREMENT MODE
PULSE-WIDTH MEASUREMENT
MODE
(2)
measurement). No noise filter on CAP1 input is used. The MOVWF instruction loads CAP1CON when W = 0111.
ture event, the write will always take precedence. All Input Capture Buffers, CAP1BUF, CAP2BUF and CAP3BUF, are
updated with the incremented value of the time base on the next T
(see
is always present on the edge that first initiates the pulse-width measurement (i.e., when configured in the rising to
falling Pulse-Width Measurement mode); it is active on each rising edge detected. In the falling to rising Pulse-Width
Measurement mode, it is active on each falling edge detected.
(3)
(see capture and Reset relationship in
(4,5)
Note 4
MOVWF CAP1CON
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PULSE-WIDTH MEASUREMENT MODE TIMING
when Reset occurs).
0012
0013
0014
PIC18F2331/2431/4331/4431
CY
rising edge. In the event that a write to TMR5 coincides with an input cap-
0015
0015
0000
Timer5 is always reset on the edge when the
measurement is first initiated. For example, when the
measurement is based on the falling to rising edge,
Timer5 is first reset on the falling edge, and thereafter,
the timer value is captured on the rising edge. Upon
entry into the Pulse-Width Measurement mode, the
very first edge detected on the CAPx pin is always
captured. The TMR5 value is reset on the first active
edge (see
0001
CY
clock edge when the capture event takes place
Figure
0002
17-5).
0001
0000
0001
DS39616D-page 157
0002
0002

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