PIC18LF2431-I/SP Microchip Technology, PIC18LF2431-I/SP Datasheet - Page 274

• Manufacturer Part Number: PIC18LF2431-I/SP
• Description: IC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2431-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 24
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

PIC18F2331/2431/4331/4431
23.2
For PIC18F2331/2431/4331/4431 devices, the WDT is
driven by the INTRC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in
Configuration
Available periods range from 4 ms to 131.072 seconds
(2.18 minutes). The WDT and postscaler are cleared
when any of the following events occur: execute a
SLEEP
(OSCCON<6:4>) are changed or a clock failure has
occurred (see
Watchdog
Adjustments to the internal oscillator clock period using
the OSCTUNE register also affect the period of the
WDT by the same factor. For example, if the INTRC
period is increased by 3%, then the WDT period is
increased by 3%.
FIGURE 23-1:
DS39616D-page 274
Change on IRCF bits
All Device Resets
Watchdog Timer (WDT)
or
INTRC Source
WDTPS<3:0>
Timer”).
CLRWDT
SWDTEN
Register
WDTEN
CLRWDT
Section 23.4.1 “FSCM and the
Sleep
WDT BLOCK DIAGRAM
instruction,
2H
(see
Enable WDT
the
Register
WDT Counter
IRCF
125
23-3).
INTRC Control
4
bits
Programmable Postscaler
1:1 to 1:32,768
23.2.1
Register 23-15
readable and writable register. The SWDTEN bit allows
software to enable or disable the WDT, but only if the
Configuration bit has disabled the WDT. The WDTW bit
is a read-only bit that indicates when the WDT count is
in the fourth quadrant (i.e., when the 8-bit WDT value is
b’11000000’ or greater).
Note 1: The CLRWDT and SLEEP instructions
2: Changing the setting of the IRCF bits
3: When a CLRWDT instruction is executed,
4: If WINEN = 0, then CLRWDT must be exe-
CONTROL REGISTER
WDT
clear the WDT and postscaler counts
when executed.
(OSCCON<6:4>) clears the WDT and
postscaler counts.
the postscaler count will be cleared.
cuted only when WDTW = 1; otherwise, a
device Reset will result.
shows the WDTCON register. This is a
Reset
 2010 Microchip Technology Inc.
Wake-up
from Sleep
WDT
Reset