PIC18LF2431-I/SP Microchip Technology, PIC18LF2431-I/SP Datasheet - Page 92

IC MCU FLASH 8KX16 28-DIP

PIC18LF2431-I/SP

Manufacturer Part Number
PIC18LF2431-I/SP
Description
IC MCU FLASH 8KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF2431-I/SP

Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
24
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
24
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
PIC18F2331/2431/4331/4431
8.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
DS39616D-page 92
Read 64 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer with address being erased.
Do the row erase procedure (see
“Flash Program Memory Erase
Load Table Pointer with the address of the first
byte being written.
Write the first 8 bytes into the holding registers
with auto-increment.
FLASH PROGRAM MEMORY WRITE
SEQUENCE
Sequence”).
Section 8.4.1
7.
8.
9.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for the duration of the write
13. Execute a NOP.
14. Re-enable interrupts.
15. Repeat Steps 6-14 seven times to write
16. Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in
Set the EECON1 register for the write operation
by doing the following:
• Set the EEPGD bit to point to program
• Clear the CFGS bit to access program
• Set the WREN bit to enable byte writes
Disable interrupts.
Write 55h to EECON2.
(about 2 ms using internal timer).
64 bytes.
memory
memory
Example
 2010 Microchip Technology Inc.
8-3.

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