PIC18LF2431-I/SP Microchip Technology, PIC18LF2431-I/SP Datasheet - Page 314

• Manufacturer Part Number: PIC18LF2431-I/SP
• Description: IC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2431-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 24
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

PIC18F2331/2431/4331/4431
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39616D-page 314
Q Cycle Activity:
After Interrupt
operation
Decode
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL
No
Q1
operation
operation
Return from Interrupt
[ label ]
s  [0,1]
(TOS)  PC,
1  GIE/GIEH or PEIE/GIEL;
if s = 1:
(WS)  W,
(STATUSS)  STATUS,
(BSRS)  BSR,
PCLATU, PCLATH are unchanged
GIE/GIEH, PEIE/GIEL.
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low-priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers, WS,
STATUSS and BSRS, are loaded into
their corresponding registers, W,
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs.
1
2
RETFIE
0000
No
No
Q2
RETFIE [s]
1
0000
operation
operation
=
=
=
=
=
No
No
Q3
TOS
WS
BSRS
STATUSS
1
0001
Set GIEH or
from stack
operation
POP PC
GIEL
No
Q4
000s
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
TABLE
Q Cycle Activity:
:
:
:
CALL TABLE ; W contains table
ADDWF PCL
RETLW k0
RETLW k1
RETLW kn
Before Instruction
After Instruction
operation
Decode
W
W
No
Q1
; offset value
; W now has
; table value
; W = offset
; Begin table
;
; End of table
=
=
operation
Return Literal to W
[ label ]
0  k  255
k  W,
(TOS)  PC,
PCLATU, PCLATH are unchanged
None
W is loaded with the 8-bit literal, ‘k’. The
program counter is loaded from the top
of the stack (the return address). The
high address latch (PCLATH) remains
unchanged.
1
2
literal ‘k’
Read
0000
No
Q2
0x07
value of kn
 2010 Microchip Technology Inc.
RETLW k
1100
operation
Process
Data
No
Q3
kkkk
from stack,
Write to W
operation
POP PC
No
Q4
kkkk