EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 243

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

ParllIfIn
DS785UM1
31
15
Address: 0x8003_005C
Default: 0x0000_0000
Definition: Parallel Interface Output/Control Register
Bit Descriptions:
30
14
29
13
28
12
This register, if PIFEN = ‘1’ in the
Smart Panel. A Smart Panel has an integrated controller and frame buffer.
RSVD:
ESTRT:
CNT:
RSVD
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
P3 --> D3
P[2:0] --> D[2:0]
SPCLK --> E
Smart Panel R/W and RS signals must be implemented
via GPIOs and controlled via software.
Reserved - Unknown during read
Enable Start - Read/Write
The Enable Signal Start Value for the parallel interface
down counter should be written to this field. When the
parallel interface counter counts down to this value during
a write cycle (see RD bit in the
cycle), the E enable signal on the E pin goes active.
The E enable signal becomes inactive just before the
counter counts down to 0x0, although data remains driven
on the D[7:0] pins throughout the 0x0 count. This allows
data to be driven for one additional clock cycle, providing
data hold time to the Smart Panel.
Count - Read/Write
The counter preload value that is written to this field gets
loaded into the parallel interface down counter. When a
write or read cycle is initiated by writing to the RD bit in the
ParllIfOut
this value.
Raster Engine With Analog/LCD Integrated Timing and Interface
24
8
register, the counter begins to count down from
23
7
VideoAttribs
22
6
ESTRT
21
5
register, is used to access a
20
4
ParllIfOut
DAT
19
3
EP93xx User’s Guide
register for write
18
2
CNT
17
1
16
7-61
0
7