EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 797

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
EGPIO[15:8]
IDEDA[2:0]
EGPIO[7:0]
DD[15:12]
ROW[7:0]
IDECS1n
IDECS0n
COL[7:0]
DD[11:8]
GRLED
RDLED
SLA[1:0]
DD[7:0]
EECLK
EEDAT
DIORn
4. EEDAT is the EEPROM data pin.
5. ROW[7:0] are the Key Matrix row pins.
6. COL[7:0] are the Key Matrix column pins.
1. IDEDA[2:0], IDECS0n, IDECS1n, and DIORn are IDE control pins.
2. DD[15:0] are the IDE data pins. DD[11:8] has no GPIO pin mapping.
3. GRLED is the Green LED pin.
4. RDLED is the Red LED pin.
5. EECLK is the EEPROM clock pin.
6. EEDAT is the EEPROM data pin.
7. ROW[7:0] are the Key Matrix row pins.
8. COL[7:0] are the Key Matrix column pins.
Name
Pin
1
5
6
3
4
2
2
8
1
1
7
2
1
IDEDA[2:0]
Function
ROW[7:0]
DD[15:12]
Port G3:2
IDECS1n
IDECS0n
COL[7:0]
Default
DD[11:8]
Port E0
Port E1
Port G0
Port G1
DD[7:0]
DIORn
Port A
Port B
Table 28-3. EP9312 GPIO Port to Pin Map
Function in
IDEDA[2:0]
DD[15:12]
Port G3:2
IDECS1n
IDECS0n
Copyright 2007 Cirrus Logic
DD[11:8]
Port G0
Port G1
Port E0
Port E1
DD[7:0]
GonK
DIORn
Mode
Port C
Port D
Port A
Port B
Function in
DD[15:12]
ROW[7:0]
Port G3:2
Port E7:5
EonIDE
COL[7:0]
DD[11:8]
Port G0
Port G1
DD[7:0]
Port E0
Port E1
Port E4
Port E3
Port E2
Mode
Port A
Port B
Function in
IDEDA[2:0]
ROW[7:0]
GonIDE
Port G3:2
IDECS1n
IDECS0n
Port G7:4
COL[7:0]
DD[11:8]
Port G0
Port G1
DD[7:0]
Port E0
Port E1
DIORn
Mode
Port A
Port B
Function in
IDEDA[2:0]
DD[15:12]
EP93xx User’s Guide
Port G3:2
ROW[7:0]
IDECS1n
IDECS0n
HonIDE
COL[7:0]
DD[11:8]
Port E0
Port E1
Port G0
Port G1
DIORn
Mode
Port A
Port B
Port H
GPIO Interface
28-7
28