EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 547

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

UART1DMACtrl
Modem Register Descriptions
UART1ModemCtrl
DS785UM1
31
15
31
15
Address:
Default:
Definition:
Bit Descriptions:
Address:
30
14
30
14
29
13
29
13
28
12
28
12
0x808C_0028 - Read/Write
0x0000_0000
UART DMA Control Register
RSVD:
DMAERR:
TXDMAE:
RXDMAE:
0x808C_0100 - Read/Write
RSVD
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
RSVD
25
25
9
9
Reserved. Unknown During Read.
RX DMA error handing enable. If 0, the RX DMA interface
ignores error conditions in the UART receive section. If 1,
the DMA interface stops and notifies the DMA block when
an error occurs. Errors include break errors, parity errors,
and framing errors.
TX DMA interface enable. Setting to 1 enables the private
DMA interface to the transmit FIFO.
RX DMA interface enable. Setting to 1 enables the private
DMA interface to the receive FIFO.
24
24
8
8
RSVD
RSVD
23
23
7
7
0
UART1 With HDLC and Modem Control Signals
22
22
6
6
0
21
21
5
5
0
LOOP
20
20
4
4
OUT2
19
19
3
3
EP93xx User’s Guide
DMAERR
OUT1
18
18
2
2
TXDMAE
RTS
17
1
17
1
RXDMAE
14-25
DTR
16
0
16
0
14