EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 39

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
2.2.1 Features
2.1 Introduction
2.2 Overview: ARM920T Core
2ARM920T Core and Advanced High-Speed Bus (AHB)
This chapter describes the ARM920T Core and the Advanced High-Speed Bus (AHB).
The ARM920T is a Harvard architecture core with separate 16 kbyte instruction and data
caches with an 8-word line length. The ARM Core utilizes a five-stage pipeline consisting of
fetch, decode, execute, data memory access, and write stages.
Key features include:
• ARM V4T (32-bit) and Thumb (16-bit compressed) instruction sets
• 32-bit Advanced Micro-Controller Bus Architecture (AMBA)
• 16 kbyte Instruction Cache with lockdown
• 16 kbyte Data Cache (programmable write-through or write-back) with lockdown
• Write Buffer
• MMU for Microsoft Windows CE and Linux operating systems
• Translation Look-aside Buffers (TLB) with 64 Data and 64 Instruction Entries
• Programmable Page Sizes of 64 kbyte, 4 kbyte, and 1 kbyte
• Independent lockdown of TLB Entries
• JTAG Interface for Debug Control
• Co-processor Interface
Copyright 2007 Cirrus Logic
Chapter 2
2-1
2