EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 630

IC ARM9 SOC PROCESSOR 208LQFP

EP9302-IQZ

Manufacturer Part Number
EP9302-IQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9302-IQZ

Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-LQFP
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
3
No. Of Pwm Channels
1
Digital Ic Case Style
LQFP
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1253

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9302-IQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
EP9302-IQZ
Manufacturer:
CIRRUS
Quantity:
20 000
17
MIIR
17-34
IrDA
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
RFC:
RFS:
TAB:
TFC:
TFS:
0x808B_0088 - Read Only
0x0000_0000
MIR Interrupt Register. The IrDA interrupt is asserted if any bit in the MIIR is
high.
RSVD:
RFL:
RIL:
RFC:
RFS:
TAB:
TFC:
TFS:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
RFC mask bit. When high, the MIR RFC status can
generate an interrupt.
RFS mask bit. When high, the MIR RFS status can
generate an interrupt.
TAB mask bit. When high, the MIR TAB status can
generate an interrupt.
TFC mask bit. When high, the MIR TFC status can
generate an interrupt.
TFS mask bit. When high, the MIR TFS status can
generate an interrupt.
Reserved. Unknown During Read.
Logical AND of MIR RFL status bit and RFL mask bit.
Logical AND of MIR RIL status bit and RIL mask bit.
Logical AND of MIR RFC status bit and RFC mask bit.
Logical AND of MIR RFS status bit and RFS mask bit.
Logical AND of MIR TAB status bit and TAB mask bit.
Logical AND of MIR TFC status bit and TFC mask bit.
Logical AND of MIR TFS status bit and TFS mask bit.
24
8
RSVD
23
7
RFL
22
6
RIL
21
5
RFC
20
4
RFS
19
3
TAB
18
2
TFC
17
1
DS785UM1
TFS
16
0

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