MC9S08EL16CTJ Freescale Semiconductor, MC9S08EL16CTJ Datasheet - Page 288
![MCU 16KB FLASH SLIC 20TSSOP](/photos/12/26/122655/mc9s08el16ctj_sml.jpg)
MC9S08EL16CTJ
Manufacturer Part Number
MC9S08EL16CTJ
Description
MCU 16KB FLASH SLIC 20TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.DEMO9S08EL32.pdf
(356 pages)
Specifications of MC9S08EL16CTJ
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
S08EL
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI, I2C, SLIC
Maximum Clock Frequency
200 KHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08EL32AUTO, DEMO9S08EL32
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
For Use With
DEMO9S08EL32 - BOARD DEMO FOR 9S08 EL MCUDEMO9S08EL32AUTO - DEMO BOARD EL32 AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Timer/PWM Module (S08TPMV3)
Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the
TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data
involved in the write.
When BDM is active, the timer counter is frozen (this is the value that will be read by user); the coherency
mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became
active, even if one or both counter halves are read while BDM is active. This assures that if the user was
in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from
the other half of the 16-bit value after returning to normal execution.
In BDM mode, writing any value to TPMxSC, TPMxCNTH or TPMxCNTL registers resets the read
coherency mechanism of the TPMxCNTH:L registers, regardless of the data involved in the write.
16.3.3
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock, and
the overflow flag (TOF) becomes set. Writing to TPMxMODH or TPMxMODL inhibits the TOF bit and
overflow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000
which results in a free running timer counter (modulo disabled).
Writing to either byte (TPMxMODH or TPMxMODL) latches the value into a buffer and the registers are
updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so:
The latching mechanism may be manually reset by writing to the TPMxSC address (whether BDM is
active or not).
290
Reset
Reset
•
•
W
W
R
R
If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written
If (CLKSB:CLKSA not = 0:0), then the registers are updated after both bytes were written, and the
TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If
the TPM counter is a free-running counter, the update is made when the TPM counter changes from
0xFFFE to 0xFFFF
Bit 15
Bit 7
TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)
0
0
7
7
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
14
0
6
0
6
6
Figure 16-8. TPM Counter Register High (TPMxCNTH)
Figure 16-9. TPM Counter Register Low (TPMxCNTL)
Any write to TPMxCNTH clears the 16-bit counter
Any write to TPMxCNTL clears the 16-bit counter
13
5
0
5
5
0
12
0
4
0
4
4
11
0
3
0
3
3
10
0
2
0
2
2
Freescale Semiconductor
1
9
0
1
1
0
Bit 8
Bit 0
0
0
0
0
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