PIC16LF819T-I/SO Microchip Technology, PIC16LF819T-I/SO Datasheet - Page 144
![IC MCU FLASH 2KX14 EEPROM 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16LF819T-I/SO
Manufacturer Part Number
PIC16LF819T-I/SO
Description
IC MCU FLASH 2KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F818-ISO.pdf
(8 pages)
4.PIC16F818-ISO.pdf
(8 pages)
5.PIC18F2450-ISO.pdf
(324 pages)
Specifications of PIC16LF819T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF819T-I/SO
Manufacturer:
MITSUBISHI
Quantity:
330
Part Number:
PIC16LF819T-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC18F2450-ISO PDF datasheet #5
- Current page: 144 of 324
- Download datasheet (6Mb)
PIC18F2450/4450
TABLE 14-4:
TABLE 14-5:
DS39760D-page 142
Legend: (E) = EVEN transaction buffer, (O) = ODD transaction buffer
BDnSTAT
BDnCNT
BDnADRL
BDnADRH
Note 1:
Endpoint
Name
2:
3:
4:
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
(1)
(1)
(1)
(1)
For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID3:PID0 values once the register
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for DTSEN and BSTALL are no longer valid.
Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 3 and 2 of the BDnSTAT
register are used to configure the DTSEN and BSTALL settings.
This bit is ignored unless DTSEN = 1.
Byte Count
Buffer Address Low
Buffer Address High
ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT
BUFFERING MODES
SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS
UOWN
Bit 7
Out
10
12
14
16
18
20
22
24
26
28
30
(No Ping-Pong)
0
2
4
6
8
Mode 0
DTS
Bit 6
(4)
13
15
17
19
21
23
25
27
29
31
11
In
1
3
5
7
9
PID3
Bit 5
0 (E), 1 (O)
(2)
(Ping-Pong on EP0 OUT)
Out
13
15
17
19
21
23
25
27
29
31
11
BDs Assigned to Endpoint
3
5
7
9
PID2
Bit 4
Mode 1
(2)
DTSEN
PID1
10
12
14
16
18
20
22
24
26
28
30
32
In
2
4
6
8
Bit 3
(2)
(3)
BSTALL
16 (E), 17 (O)
40 (E), 41 (O)
44 (E), 45 (O)
48 (E), 49 (O)
52 (E), 53 (O)
56 (E), 57 (O)
60 (E), 61 (O)
12 (E), 13 (O)
20 (E), 21 (O)
24 (E), 25 (O)
28 (E), 29 (O)
32 (E), 33 (O)
36 (E), 37 (O)
PID0
0 (E), 1 (O)
4 (E), 5 (O)
8 (E), 9 (O)
Bit 2
(Ping-Pong on all EPs)
Out
© 2008 Microchip Technology Inc.
(2)
(3)
Mode 2
Bit 1
BC9
14 (E), 15 (O)
18 (E), 19 (O)
22 (E), 23 (O)
26 (E), 27 (O)
34 (E), 35 (O)
38 (E), 39 (O)
42 (E), 43 (O)
46 (E), 47 (O)
50 (E), 51 (O)
54 (E), 55 (O)
58 (E), 59 (O)
62 (E), 63 (O)
10 (E), 11 (O)
30 (E), 31 (O)
2 (E), 3 (O)
6 (E), 7 (O)
In
Bit 0
BC8
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