PIC16LF819T-I/SO Microchip Technology, PIC16LF819T-I/SO Datasheet - Page 77
![IC MCU FLASH 2KX14 EEPROM 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16LF819T-I/SO
Manufacturer Part Number
PIC16LF819T-I/SO
Description
IC MCU FLASH 2KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F818-ISO.pdf
(8 pages)
4.PIC16F818-ISO.pdf
(8 pages)
5.PIC18F2450-ISO.pdf
(324 pages)
Specifications of PIC16LF819T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF819T-I/SO
Manufacturer:
MITSUBISHI
Quantity:
330
Part Number:
PIC16LF819T-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC18F2450-ISO PDF datasheet #5
- Current page: 77 of 324
- Download datasheet (6Mb)
REGISTER 6-1:
© 2008 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
When a WRERR occurs, the CFGS bit is not cleared. This allows tracing of the error condition.
Unimplemented: Read as ‘0’
CFGS: Flash Program or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write-only
WRERR: Flash Program Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
0 = The write operation completed
WREN: Flash Program Write Enable bit
1 = Allows write cycles to Flash program
0 = Inhibits write cycles to Flash program
WR: Write Control bit
1 = Initiates a program memory erase cycle or write cycle
0 = Write cycle complete
Unimplemented: Read as ‘0’
CFGS
R/W-x
(cleared by completion of erase operation)
operation or an improper write attempt)
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
EECON1: MEMORY CONTROL REGISTER 1
S = Settable bit
W = Writable bit
‘1’ = Bit is set
U-0
—
R/W-0
FREE
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WRERR
R/W-x
(1)
PIC18F2450/4450
WREN
R/W-0
x = Bit is unknown
R/S-0
WR
DS39760D-page 75
U-0
—
bit 0
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