PIC16LF819T-I/SO Microchip Technology, PIC16LF819T-I/SO Datasheet - Page 226
![IC MCU FLASH 2KX14 EEPROM 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16LF819T-I/SO
Manufacturer Part Number
PIC16LF819T-I/SO
Description
IC MCU FLASH 2KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F818-ISO.pdf
(8 pages)
4.PIC16F818-ISO.pdf
(8 pages)
5.PIC18F2450-ISO.pdf
(324 pages)
Specifications of PIC16LF819T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF819T-I/SO
Manufacturer:
MITSUBISHI
Quantity:
330
Part Number:
PIC16LF819T-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC18F2450-ISO PDF datasheet #5
- Current page: 226 of 324
- Download datasheet (6Mb)
PIC18F2450/4450
BNOV
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39760D-page 224
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Overflow
If Overflow
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Overflow
BNOV
-128 ≤ n ≤ 127
if Overflow bit is ‘0’,
(PC) + 2 + 2n → PC
None
If the Overflow bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
n
0101
BNOV Jump
operation
Process
Process
Data
Data
No
Q3
Q3
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
BNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Zero
If Zero
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Zero
BNZ
-128 ≤ n ≤ 127
if Zero bit is ‘0’,
(PC) + 2 + 2n → PC
None
If the Zero bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
‘n’
‘n’
Q2
Q2
=
=
=
=
=
© 2008 Microchip Technology Inc.
n
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
0001
BNZ
operation
Process
Process
Data
Data
No
Q3
Q3
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
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