PIC16LF819T-I/SO Microchip Technology, PIC16LF819T-I/SO Datasheet - Page 168
![IC MCU FLASH 2KX14 EEPROM 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16LF819T-I/SO
Manufacturer Part Number
PIC16LF819T-I/SO
Description
IC MCU FLASH 2KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F818-ISO.pdf
(8 pages)
4.PIC16F818-ISO.pdf
(8 pages)
5.PIC18F2450-ISO.pdf
(324 pages)
Specifications of PIC16LF819T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF819T-I/SO
Manufacturer:
MITSUBISHI
Quantity:
330
Part Number:
PIC16LF819T-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC18F2450-ISO PDF datasheet #5
- Current page: 168 of 324
- Download datasheet (6Mb)
PIC18F2450/4450
FIGURE 15-7:
TABLE 15-6:
DS39760D-page 166
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note:
Name
RX (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word
causing the OERR (Overrun Error) bit to be set.
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
SPEN
CSRC
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
—
—
—
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 1
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
bit 7/8
Stop
INT0IE
CREN
SYNC
SCKP
bit
Bit 4
TXIF
TXIE
TXIP
Word 1
RCREG
Start
bit
ADDEN
SENDB
bit 0
BRG16
RBIE
Bit 3
—
—
—
TMR0IF
CCP1IE
CCP1IP
CCP1IF
bit 7/8
BRGH
FERR
Word 2
RCREG
Bit 2
—
Stop
bit
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
Start
WUE
© 2008 Microchip Technology Inc.
Bit 1
bit
TMR1IF
TMR1IE
TMR1IP
ABDEN
RX9D
TX9D
bit 7/8
RBIF
Bit 0
Stop
bit
on Page:
Values
Reset
49
51
51
51
51
50
51
51
50
50
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