PIC16LF819T-I/SO Microchip Technology, PIC16LF819T-I/SO Datasheet - Page 145
![IC MCU FLASH 2KX14 EEPROM 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16LF819T-I/SO
Manufacturer Part Number
PIC16LF819T-I/SO
Description
IC MCU FLASH 2KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F818-ISO.pdf
(8 pages)
4.PIC16F818-ISO.pdf
(8 pages)
5.PIC18F2450-ISO.pdf
(324 pages)
Specifications of PIC16LF819T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF819T-I/SO
Manufacturer:
MITSUBISHI
Quantity:
330
Part Number:
PIC16LF819T-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC18F2450-ISO PDF datasheet #5
- Current page: 145 of 324
- Download datasheet (6Mb)
14.5
The USB module can generate multiple interrupt
conditions. To accommodate all of these interrupt
sources, the module is provided with its own interrupt
logic structure, similar to that of the microcontroller.
USB interrupts are enabled with one set of control regis-
ters and trapped with a separate set of flag registers. All
sources are funneled into a single USB interrupt
request, USBIF (PIR2<5>), in the microcontroller’s
interrupt logic.
FIGURE 14-8:
FIGURE 14-9:
© 2008 Microchip Technology Inc.
Note
Differential Data
USB Interrupts
1:
UEIR (Flag) and UEIE (Enable) Registers
The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
USB Reset
CRC5EE
URSTIF
CRC5EF
RESET
BTOEE
BTOEF
BTSEF
BTSEE
Second Level USB Interrupts
PIDEE
PIDEF
CRC16EE
CRC16EF
DFN8EE
DFN8EF
Start-of-Frame (SOF)
(USB Error Conditions)
USB INTERRUPT LOGIC FUNNEL
EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
SOFIF
SOF
SETUP
DATA
STATUS
STALLIF
STALLIE
UERRIE
UERRIF
ACTVIE
URSTIE
ACTVIF
URSTIF
IDLEIF
IDLEIE
SOFIF
SOFIE
TRNIE
TRNIF
Figure 14-8 shows the interrupt logic for the USB
module. There are two layers of interrupt registers in
the USB module. The top level consists of overall USB
status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second level
consists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. An
interrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.
Interrupts may be used to trap routine events in a USB
transaction. Figure 14-9 shows some common events
within a USB frame and their corresponding interrupts.
SETUP Token
OUT Token
Control Transfer
UIR (Flag) and UIE (Enable) Registers
From Host
IN Token
From Host
From Host
Top Level USB Interrupts
(USB Status Interrupts)
PIC18F2450/4450
Empty Data
Transaction
From Host
From Host
To Host
(1)
Data
Data
From Host
To Host
To Host
ACK
ACK
ACK
SOF
USBIF
1 ms Frame
DS39760D-page 143
Set TRNIF
Set TRNIF
Set TRNIF
Transaction
Complete
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