PIC16LF819T-I/SO Microchip Technology, PIC16LF819T-I/SO Datasheet - Page 209
![IC MCU FLASH 2KX14 EEPROM 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16LF819T-I/SO
Manufacturer Part Number
PIC16LF819T-I/SO
Description
IC MCU FLASH 2KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F818-ISO.pdf
(8 pages)
4.PIC16F818-ISO.pdf
(8 pages)
5.PIC18F2450-ISO.pdf
(324 pages)
Specifications of PIC16LF819T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF819T-I/SO
Manufacturer:
MITSUBISHI
Quantity:
330
Part Number:
PIC16LF819T-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC18F2450-ISO PDF datasheet #5
- Current page: 209 of 324
- Download datasheet (6Mb)
FIGURE 18-4:
18.4.3
By entering a power-managed mode, the clock multi-
plexer selects the clock source selected by the OSCCON
register. Fail-Safe Clock Monitoring of the power-
managed clock source resumes in the power-managed
mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTRC. An automatic transition back to the failed
clock source will not occur.
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTRC source.
18.4.4
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
device clock is either EC or INTRC, monitoring can
begin immediately following these events.
For oscillator modes involving a crystal or resonator
(HS, HSPLL or XT), the situation is somewhat different.
Since the oscillator may require a start-up time
© 2008 Microchip Technology Inc.
Note:
Sample Clock
CM Output
FSCM INTERRUPTS IN
POWER-MANAGED MODES
POR OR WAKE-UP FROM SLEEP
OSCFIF
Device
Output
Clock
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this
example have been chosen for clarity.
(Q)
FSCM TIMING DIAGRAM
CM Test
considerably longer than the FCSM sample clock time,
a false clock failure may be detected. To prevent this,
the internal oscillator is automatically configured as the
device clock and functions until the primary clock is
stable (the OST and PLL timers have timed out). This
is identical to Two-Speed Start-up mode. Once the
primary clock is stable, the INTRC returns to its role as
the FSCM source.
As noted in Section 18.3.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alternate
power-managed mode while waiting for the primary
clock to become stable. When the new power-managed
mode is selected, the primary clock is disabled.
Note:
CM Test
Oscillator
Failure
PIC18F2450/4450
The same logic that prevents false oscilla-
tor failure interrupts on POR or wake from
Sleep will also prevent the detection of the
oscillator’s failure to start at all following
these events. This can be avoided by
monitoring the OSTS bit and using a
timing routine to determine if the oscillator
is taking too long to start. Even so, no
oscillator failure interrupt will be flagged.
Detected
Failure
CM Test
DS39760D-page 207
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