PIC16F689-I/ML Microchip Technology, PIC16F689-I/ML Datasheet - Page 198

• Manufacturer Part Number: PIC16F689-I/ML
• Description: IC PIC MCU FLASH 4KX14 20QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F689-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 18
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SPI/SSP/EUSART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163029, DM164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PIN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F631/677/685/687/689/690
14.2
The PIC16F631/677/685/687/689/690 differentiates
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
• Power-on Reset
• MCLR Reset
• MCLR Reset during Sleep
• WDT Reset
• Brown-out Reset (BOR)
FIGURE 14-1:
DS41262D-page 196
MCLR/V
Power-on Reset (POR)
WDT Reset during normal operation
WDT Reset during Sleep
Brown-out Reset (BOR)
MCLR Reset during normal operation
MCLR Reset during Sleep
CLKI pin
OSC1/
Note 1:
V
DD
Reset
PP
pin
LFINTOSC
OST/PWRT
Refer to the Configuration Word register (Register 14-1).
Brown-out
V
Module
Detect
DD
WDT
Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Rise
OST
PWRT
(1)
10-bit Ripple Counter
WDT
Time-out
Reset
11-bit Ripple Counter
SBOREN
BOREN
Power-on Reset
External
Reset
Sleep
They are not affected by a WDT Wake-up since this is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
situations, as indicated in Table 14-2. These bits are
used in software to determine the nature of the Reset.
See Table 14-4 for a full description of Reset states of
all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 14-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 17.0 “Electrical
Specifications” for pulse-width specifications.
Enable PWRT
Enable OST
© 2007 Microchip Technology Inc.
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R
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Chip_Reset