ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 103

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9132D–AUTO–12/10
RXD: UART Receive pin. When the UART receiver is enabled, this pin is configured as an
RXLIN: LIN Receive pin. When the LIN is enabled, this pin is configured as an input regardless
Table 4-25
shown in
Table 4-25.
Signal
DIEOE
DIEOV
DDOE
PUOE
PUOV
DDOV
PVOE
Name
PVOV
PTOE
AIO
DI
input regardless of the value of DDA0. When the pin is forced to be an input, a logical
one in PORTA0 will turn on the internal pull-up.
of the value of DDA0. When the pin is forced to be an input, a logical one in PORTA0 will
turn on the internal pull-up.
ADC7 -/- AIN1 -/-
Figure 4-29 on page
XREF -/- AREF
PA7/PCINT7/
/XREF/AREF
ADC7/AIN1
and
PCMSK07)
PCMSK07
(PCIE0 &
ADC7D |
PCIE0 &
PCINT7
Overriding Signals for Alternate Functions in PA7..PA4
Table 4-26
0
0
0
0
0
0
0
PORTA6 & PUD
relate the alternate functions of Port A to the overriding signals
ADC6/AIN0/SS
PCINT6 -/- SS
ADC6 -/- AIN0
SPE & MSTR
SPE & MSTR
PA6/PCINT6/
97.
PCMSK06)
PCMSK06
(PCIE0 &
ADC6D |
PCIE0 &
0
0
0
0
(USI_2_WIRE & USIPOS)
Atmel ATA6616/ATA6617
(USI_2_WIRE & USIPOS
-/- USCK -/- SCL -/- SCK
USI_PTOE & USIPOS
(USISIE & USIPOS) |
(PCIE0 & PCMSK05)
(USISIE & USIPOS) |
(PCIE0 & PCMSK05)
PA5/PCINT5/ADC5/
T1/USCK/SCL/SCK
{ (SPE & MSTR) ?
(USI_SCL_HOLD |
~ (USI_2_WIRE &
(SCK_OUTPUT) :
PORTA5 & PUD
(SPE & MSTR) |
(SPE & MSTR) |
PCINT5 -/- T1
SPE & MSTR
& DDRA5) }
& DDRA5)
& DDRA6
PORTA5)
ADC5D |
USIPOS
ADC5
(USI_2_WIRE & USIPOS
-/- DI -/- SDA -/- MOSI
(USISIE & USIPOS) |
(PCIE0 & PCMSK04)
(USISIE & USIPOS) |
(PCIE0 & PCMSK04)
PA4/PCINT4/ADC4/
ICP1/DI/SDA/MOSI
{ (SPE & MSTR) ?
{ (SPE & MSTR) ?
(MOSI_OUTPUT) :
~ (USI_2_WIRE &
(USI_SHIFTOUT |
(SPE & MSTR) |
(SPE & MSTR) |
PORTA4 & PUD
(USI_2_WIRE &
PCINT4 -/- ICP1
SPE & MSTR
& DDRA4) }
& DDRA4) }
& DDRA4)
USIPOS)
PORTA4)
ADC4D |
USIPOS
ADC4
(0) :
0
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