ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 37

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.7
4.3.7.1
9132D–AUTO–12/10
Reset and Interrupt Handling
Interrupt behavior
The AVR
Reset Vector each have a separate Program Vector in the Program memory space. All inter-
rupts are assigned individual enable bits which must be written logic one together with the
Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
The list also determines the priority levels of the different interrupts. The lower the address the
higher is the priority level. RESET has the highest priority, and next is INT0 – the External
Interrupt Request 0.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All
enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set
when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt
Vector in order to execute the interrupt handling routine, and hardware clears the correspond-
ing Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit
position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt
enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is
enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur
while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set
and remembered until the Global Interrupt Enable bit is set, and will then be executed by order
of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before
the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute
one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine,
nor restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately dis-
abled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously
with the CLI instruction. The following example shows how this can be used to avoid interrupts
during the timed EEPROM write sequence.
®
provides several different interrupt sources. These interrupts and the separate
Atmel ATA6616/ATA6617
Section 4.8 “Interrupts” on page
82.
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