ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 128

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.11.11.6
128
Atmel ATA6616/ATA6617
Timer/Counter
0
• Bit 1 – TCR0AUB: Timer/Counter0 Control Register A Update Busy
When Timer/Counter0 operates asynchronously and TCCR0A is written, this bit becomes set.
When TCCR0A has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR0A is ready to be updated with a new
value.
• Bit 0 – TCR0BUB: Timer/Counter0 Control Register B Update Busy
When Timer/Counter0 operates asynchronously and TCCR0B is written, this bit becomes set.
When TCCR0B has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR0B is ready to be updated with a new
value.
If a write is performed to any of the four Timer/Counter0 Registers while its update busy flag is
set, the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT0, OCR0A, TCCR0A and TCCR0B are different. When
reading TCNT0, the actual timer value is read. When reading OCR0A, TCCR0A or TCCR0B
the value in the temporary storage register is read.
• Bit 7:2 – Res: Reserved Bits
These bits are reserved in the Atmel
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is exe-
cuted if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter0 Inter-
rupt Flag Register – TIFR0.
Bit
Read/Write
Initial Value
Interrupt Mask Register – TIMSK0
R
7
–
0
R
6
–
0
R
5
–
0
®
ATtiny87/167 and will always read as zero.
R
4
–
0
R
3
–
0
R
2
–
0
OCIE0A
R/W
1
0
TOIE0
R/W
0
0
9132D–AUTO–12/10
TIMSK0