ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 94

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ATA6617-P3QW

Manufacturer Part Number
ATA6617-P3QW
Description
MCU W/LIN TX/5V REG/WTCDG 38VQFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet

Specifications of ATA6617-P3QW

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATA6617-P3QW
Manufacturer:
ATMEL
Quantity:
3 500
Part Number:
ATA6617-P3QW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
94
Atmel ATA6616/ATA6617
Consider the clock period starting shortly after the first falling edge of the system clock. The
latch is closed when the clock is low, and goes transparent when the clock is high, as indi-
cated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the
system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock
edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin
will be delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in
the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
Figure 4-28. Synchronization when Reading a Software Assigned Pin Value
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and
define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The result-
ing pin values are read back again, but as previously discussed, a nop instruction is included
to be able to read back the value recently assigned to some of the pins.
Figure
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
4-28. The out instruction sets the “SYNC LATCH” signal at the positive edge of
PINxn
r16
r17
out PORTx, r16
0xFF
0x00
nop
t
pd
in r17, PINx
0xFF
9132D–AUTO–12/10

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