ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 231

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.18.12.2
9132D–AUTO–12/10
ADCSRA – ADC Control and Status Register A
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running
mode, write this bit to one to start the first conversion. The first conversion after ADSC has
been written after the ADC has been enabled, or if ADSC is written at the same time as the
ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion
performs initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is com-
plete, it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a
conversion on a positive edge of the selected trigger signal. The trigger source is selected by
setting the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ADIF is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a
Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the
SBI and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete
Interrupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input
clock to the ADC.
Bit
Read/Write
Initial Value
ADEN
R/W
7
0
ADSC
R/W
6
0
ADATE
R/W
5
0
ADIF
R/W
4
0
Atmel ATA6616/ATA6617
ADIE
R/W
3
0
ADPS2
R/W
2
0
ADPS1
R/W
1
0
ADPS0 ADCSRA
R/W
0
0
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