ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 208

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.16.6.5
4.16.6.6
208
Atmel ATA6616/ATA6617
LIN Bit Timing Register - LINBTR
LIN Baud Rate Register - LINBRR
• Bit 2 - LPERR: Parity Error Flag
• Bit 1 - LCERR: Checksum Error Flag
• Bit 0 - LBERR: Bit Error Flag
• Bit 7 - LDISR: Disable Bit Timing Re synchronization
• Bits 5:0 - LBT[5:0]: LIN Bit Timing
• Bits 15:12 - Reserved Bits
• Bits 11:0 - LDIV[11:0]: Scaling of clk
Initial Value
Initial Value
Read/Write
Read/Write
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
This bit is cleared when LERR bit in LINSIR is cleared.
Gives the number of samples of a bit.
sample-time = (1 /
Default value: LBT[6:0]=32 — Min. value: LBT[6:0]=8 — Max. value: LBT[6:0]=63
These bits are reserved for future use. For compatibility with future devices, they must be
written to zero when LINBRR is written.
The LDIV value is used to scale the entering clk
UART baud rate.
Bit
Bit
Bit
– 0 = No error,
– 1 = Parity error.
– 0 = No error,
– 1 = Checksum error.
– 0 = no error,
– 1 = Bit error.
– 0 = Bit timing re-synchronization enabled (default),
– 1 = Bit timing re-synchronization disabled.
LDISR
LDIV7
R/W
R/W
15
7
0
7
0
-
f
LDIV6
clk
R/W
14
R
6
0
6
0
-
-
i/o
) x (LDIV[11..0] + 1)
LDIV5
LBT5
R/(W)
R/W
13
5
1
5
0
-
i/o
LDIV4
LBT4
R/(W)
R/W
12
4
0
Frequency
4
0
-
LDIV11
LBT3
R/(W)
LDIV3
R/W
11
3
0
i/o
3
0
frequency to achieve appropriate LIN or
R/(W)
LBT2
LDIV10
LDIV2
R/W
2
0
10
2
0
R/(W)
LBT1
LDIV1
LDIV9
R/W
1
0
1
9
0
LBT0
R/(W)
LDIV0
LDIV8
R/W
0
9132D–AUTO–12/10
0
0
8
0
LINBRRL
LINBRRH
LINBTR