PIC16C781T-I/SO Microchip Technology, PIC16C781T-I/SO Datasheet - Page 130

• Manufacturer Part Number: PIC16C781T-I/SO
• Description: IC MCU CMOS 8BIT 1K 20MHZ 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C781T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• For Use With: AC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: PIC16C781TI/SO

PIC16C781/782
14.9
The devices have up to eight sources of interrupt. The
interrupt control register (INTCON) records individual
interrupt requests in flag bits. It also has individual and
global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT/AN4/V
rupt-on-Change (IOCB) and the TMR0 overflow inter-
rupt flags are contained in the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function register PIR1. The corresponding interrupt
enable bits are contained in special function register
PIE1, and the peripheral interrupt enable bit is con-
tained in special function register INTCON.
FIGURE 14-10:
DS41171A-page 128
Note:
Interrupts
Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
LVDIF
LVDIE
C2IF
C2IE
C1IF
C1IE
ADIF
ADIE
TMR1IF
TMR1IE
R
pin interrupt, the RB port Inter-
INTERRUPT LOGIC
Preliminary
T0IF
T0IE
INTF
INTE
RBIF
RBIE
PEIF
PEIE
GIE
When an interrupt is serviced, the GIE bit is cleared to
disable any further interrupt. The return address is
pushed onto the stack and the PC is loaded with 0004h.
Once in the Interrupt Service Routine the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in soft-
ware before re-enabling interrupts to avoid recursive
interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency is three
or four instruction cycles. The exact latency depends
on when the interrupt event occurs. The latency is the
same for one or two-cycle instructions. Individual inter-
rupt flag bits are set, regardless of the status of their
corresponding mask bit or the GIE bit.
14.9.1
External interrupt on RB0/INT/AN4/V
gered: either rising, if bit INTEDG (OPTION_REG<6>)
is set, or falling, if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can awaken the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE decides whether or not the pro-
cessor branches to the interrupt vector following a
wake-up sequence. See Section 14.12 for details on
SLEEP mode.
INT INTERRUPT
Wake-up (If in SLEEP mode)
2001 Microchip Technology Inc.
Interrupt to CPU
R
pin is edge trig-