PIC16C781T-I/SO Microchip Technology, PIC16C781T-I/SO Datasheet - Page 38

• Manufacturer Part Number: PIC16C781T-I/SO
• Description: IC MCU CMOS 8BIT 1K 20MHZ 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C781T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• For Use With: AC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: PIC16C781TI/SO

PIC16C781/782
REGISTER 3-2:
REGISTER 3-3:
3.3.3
The ANSEL and TRISB registers are the primary con-
trols for the configuration of PORTB pins. TRISB tri-
states the output drivers of PORTB, and the ANSEL
register disables the input buffers. It is important to pro-
gram both registers when configuring a port pin, since
most peripherals do not have precedence over the
TRISB and ANSEL registers’ control of the pin. Even if
a peripheral has the ability to override the control of the
TRISB and ANSEL registers, it is good practice to pro-
gram both registers appropriately.
DS41171A-page 36
bit 7-0
bit 7-0
TRISB, ANSEL, AND CONTROL
PRECEDENCE
WEAK PULL-UP PORTB REGISTER (WPUB: 95h)
WPUB<7:0>: PORTB Weak Pull-Up Control bits
1 = Weak pull-up enabled for corresponding pin
0 = Weak pull-up disabled for corresponding pin
Note 1: For the WPUB register setting to take effect, the RBPU bit in the OPTION_REG
INTERRUPT-ON-CHANGE PORTB REGISTER (IOCB: 96h)
IOCB<7:0>: Interrupt-on-Change PORTB Control bits
1 = Interrupt-on-change enabled for corresponding pin
0 = Interrupt-on-change disabled for corresponding pin
Note 1: The interrupt enable bits, GIE and RBIE in the INTCON register, must be set for indi-
bit7
Legend:
R = Readable bit
- n = Value at POR
bit7
Legend:
R = Readable bit
- n = Value at POR
WPUB7
IOCB7
R/W-1
R/W-1
2: The weak pull-up device is automatically disabled if the pin is in output mode, i.e.,
register must be cleared.
(TRISB = 0) for corresponding pin.
vidual interrupts to be recognized.
WPUB6
IOCB6
R/W-1
R/W-1
WPUB5
IOCB5
R/W-1
R/W-1
Preliminary
W = Writable bit
’1’ = Bit is set
W = Writable bit
’1’ = Bit is set
WPUB4
IOCB4
R/W-1
R/W-1
Note 1: Upon RESET, the ANSEL register config-
WPUB3
IOCB3
R/W-1
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
2: When programmed as analog inputs,
3: There are specific cases in which the
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
ures the RB<3:0> pins as analog inputs.
RB<3:0> pins will read as ‘0’.
functions of the TRISB and ANSEL regis-
ters can be overridden by a peripheral or
configuration
through Figure 3-16 for details).
WPUB2
IOCB2
R/W-1
R/W-0
2001 Microchip Technology Inc.
word
WPUB1
x = Bit is unknown
x = Bit is unknown
IOCB1
R/W-1
R/W-0
(see
Figure 3-9
WPUB0
IOCB0
R/W-1
R/W-0
bit0
bit0