PIC16C781T-I/SO Microchip Technology, PIC16C781T-I/SO Datasheet - Page 65

• Manufacturer Part Number: PIC16C781T-I/SO
• Description: IC MCU CMOS 8BIT 1K 20MHZ 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C781T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• For Use With: AC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: PIC16C781TI/SO

8.0
The PLVD module monitors the V
the microcontroller and signals the microcontroller
whenever V
acts as an ‘early warning’ of power-down, allowing the
microcontroller to finish any critical ‘housekeeping’
tasks prior to completing power-down.
Figure 8-1 demonstrates a potential application of the
PLVD module (typical battery operation). At time T
V
erence voltage. The PLVD voltage comparator then
sets the LVDIF bit (PIR<7>), indicating a low voltage
FIGURE 8-1:
8.1
The PLVD module is controlled via the LVDCON regis-
ter shown in Register 8-1.
To enable the module for testing, the LVDEN bit
(LVDCON<4>) must be set. This will enable the on-
board voltage reference and connect the resistor lad-
der between V
the module and disconnect the resistor ladder from
Vss.
DD
2001 Microchip Technology Inc.
supply voltage (V
PROGRAMMABLE LOW
VOLTAGE DETECT MODULE
(PLVD)
Control Register
DD
DD
drops below its trip voltage. The signal
and Vss. Clearing LVDEN will disable
V
V
A
B
A
TYPICAL LOW VOLTAGE DETECT APPLICATION
) has fallen below the PLVD ref-
DD
power supply of
Time
T
A
A
, the
Preliminary
T
B
condition. The time between T
to the microcontroller for completing a ‘graceful’ power-
down before V
Figure 8-2 is a simplified block diagram for the PLVD
module, showing the V
ter, and voltage comparator.
The trip voltage is set by programming the LVDL<3:0>
bit (LVDCON<3.0>). The voltages available are listed
in Register 8-1. Note that voltages below 2.5V and
above 4.75V are not available and should not be used.
The BGST bit (LVDCON<5>) is a status bit indicating
that the internal reference voltage bandgap has stabi-
lized. No test should be performed until this bit is set.
The low voltage output flag for the PLVD module is the
LVDIF bit (PIR1<6>).
Note:
Legend:
For low power applications, current drain
can be minimized by enabling the module
only during regular polled testing. When
not in use, the module is disabled by clear-
ing the LVDEN bit (LVDCON<4>), which
also powers down the resistor ladder
between V
V
V
A
B
DD
= PLVD trip point
= Minimum valid device
PIC16C781/782
operating voltage
falls below V
DD
DD
and Vss.
resistor ladder, control regis-
A
B
and T
.
DS41171A-page 63
B
is then available