ATXMEGA16A4-CUR Atmel, ATXMEGA16A4-CUR Datasheet - Page 137

MCU AVR 16+4KB FLASH 49VFBGA

ATXMEGA16A4-CUR

Manufacturer Part Number
ATXMEGA16A4-CUR
Description
MCU AVR 16+4KB FLASH 49VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheets

Specifications of ATXMEGA16A4-CUR

Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA16A4-CUR
Manufacturer:
Atmel
Quantity:
10 000
13.10 Slew-rate Control
13.11 Clock and Event Output
8077H–AVR–12/09
Figure 13-10. Port override signals and related logic
Slew-rate control can be enabled for all I/O pins individually. Enabling the slew rate limiter will
typically increase the rise/fall time by 50-150% depending on voltage, temperature and load. For
information about the characteristics of the slew-rate limiter, please refer to the device data
sheet.
It is possible to output both the Peripheral Clock and the signaling event from Event Channel 0
to pin. Output port pin is selected from software. If an event occur on Event Channel 0, this will
PINnCTRL
D
D
D
Q
OUTn
DIRn
INn
R
R
R
R
Synchronizer
Analog Input/Output
Q
Q
Q
D
Digital Input Pin
Q
OUT Override Value
OUT Override Enable
R
DIR Override Value
DIR Override Enable
D
Pull Enable
Pull Keep
Pull Direction
Digital Input Disable (DID)
Wired AND/OR
Slew Rate Limit
Inverted I/O
DID Override Value
DID Override Enable
XMEGA A
Pxn
137

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