ATXMEGA16A4-CUR Atmel, ATXMEGA16A4-CUR Datasheet - Page 146

• Manufacturer Part Number: ATXMEGA16A4-CUR
• Description: MCU AVR 16+4KB FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA16A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.16 Register Description – Virtual Port
13.16.1
13.16.2
13.16.3
8077H–AVR–12/09
DIR - Data Direction
OUT - Data Output Value
IN - Data Input Value
Table 13-8.
• Bit 7:0 - DIR[7:0]: Data Direction Register
This register sets the data direction for the individual pins in the port mapped by "VPCTRLA -
Virtual Port-map Control Register A" or "VPCTRLB - Virtual Port-map Control Register B". When
a port is mapped as virtual, accessing this register is identical to accessing the actual DIR regis-
ter for the port.
• Bit 7:0 - OUT[7:0]: Data Output value
This register sets the data output value for the individual pins in the port mapped by "VPCTRLA
- Virtual Port-map Control Register A" or "VPCTRLB - Virtual Port-map Control Register B".
When a port is mapped as virtual, accessing this register is identical to accessing the actual
OUT register for the port.
Bit
+0x02
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
CLKOUT[1:0]
00
01
10
11
Bit
+0x00
Read/Write
Initial Value
R/W
R/W
R/W
7
0
7
0
7
0
Clock output configurations
R/W
R/W
R/W
6
0
6
0
6
0
Group Configuration
OFF
PC7
PD7
PE7
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
OUT[7:0]
DIR[7:0]
IN[7:0]
Description
Clock out disabled
Clock output on Port C pin 7
Clock output on Port D pin 7
Clock output on Port E pin 7
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
XMEGA A
R/W
R/W
R/W
0
0
0
0
0
0
OUT
DIR
IN
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