PIC18F67K22-I/PTRSL Microchip Technology, PIC18F67K22-I/PTRSL Datasheet - Page 123
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F67K22-I/PTRSL
Manufacturer Part Number
PIC18F67K22-I/PTRSL
Description
MCU PIC 128K FLASH XLP 64TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F65K22T-IPTRSL.pdf
(548 pages)
3.PIC18F65K22T-IPTRSL.pdf
(10 pages)
Specifications of PIC18F67K22-I/PTRSL
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
3862Byte
Cpu Speed
16MIPS
No. Of Timers
11
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F722-ISS PDF datasheet
- PIC18F65K22T-IPTRSL PDF datasheet #2
- PIC18F65K22T-IPTRSL PDF datasheet #3
- Current page: 123 of 548
- Download datasheet (5Mb)
8.6.1
Figure 8-1 shows an example of 16-Bit Byte Write
mode for PIC18F87K22 family devices. This mode is
used for two separate 8-bit memories connected for
16-bit operation. This generally includes basic EPROM
and Flash devices. It allows table writes to byte-wide
external memories.
FIGURE 8-1:
2010 Microchip Technology Inc.
Note 1:
PIC18F87K22
2:
16-BIT BYTE WRITE MODE
A<19:16>
AD<15:8>
AD<7:0>
Upper order address lines are used only for 20-bit address widths.
This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
WRH
WRL
ALE
CE
OE
(1)
16-BIT BYTE WRITE MODE EXAMPLE
373
373
Preliminary
D<7:0>
A<19:0>
D<15:8>
PIC18F87K22 FAMILY
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD<15:0> bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
A<x:0>
D<7:0>
CE
OE
(MSB)
WR
(2)
Address Bus
Data Bus
Control Lines
D<7:0>
DS39960B-page 123
OE
A<x:0>
D<7:0>
CE
(LSB)
WR
(2)
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