PIC18F67K22-I/PTRSL Microchip Technology, PIC18F67K22-I/PTRSL Datasheet - Page 186
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F67K22-I/PTRSL
Manufacturer Part Number
PIC18F67K22-I/PTRSL
Description
MCU PIC 128K FLASH XLP 64TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F65K22T-IPTRSL.pdf
(548 pages)
3.PIC18F65K22T-IPTRSL.pdf
(10 pages)
Specifications of PIC18F67K22-I/PTRSL
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
3862Byte
Cpu Speed
16MIPS
No. Of Timers
11
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F722-ISS PDF datasheet
- PIC18F65K22T-IPTRSL PDF datasheet #2
- PIC18F65K22T-IPTRSL PDF datasheet #3
- Current page: 186 of 548
- Download datasheet (5Mb)
PIC18F87K22 FAMILY
TABLE 12-17: PORTJ FUNCTIONS
TABLE 12-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
DS39960B-page 186
RJ0
RJ1/ALE
RJ2/OE
RJ3/WRL
RJ4/WRH
RJ5/CE
RJ6/LB
RJ7/UB
Legend:
PORTJ
LATJ
TRISJ
PADCFG1
Legend: Shaded cells are not used by PORTJ.
Note 1:
Pin Name
Name
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Unimplemented on PIC18F6XK22 devices, read as ‘0’.
Function
TRISJ7
LATJ7
RDPU
Bit 7
WRH
RJ7
WRL
ALE
RJ0
RJ1
RJ2
RJ3
RJ4
RJ5
RJ6
RJ7
OE
CE
UB
LB
Setting
TRISJ6
LATJ6
REPU
TRIS
Bit 6
RJ6
0
1
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
RJPU
TRISJ5
LATJ5
Bit 5
RJ5
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
(1)
I/O
ST
ST
ST
ST
ST
ST
ST
ST
Preliminary
TRISJ4
LATJ<0> data output.
PORTJ<0> data input.
LATJ<1> data output.
PORTJ<1> data input.
External memory interface address latch enable control output. Takes
priority over digital I/O.
LATJ<2> data output.
PORTJ<2> data input.
External memory interface output enable control output. Takes priority
over digital I/O.
LATJ<3> data output.
PORTJ<3> data input.
External memory bus write low-byte control. Takes priority over digital
I/O.
LATJ<4> data output.
PORTJ<4> data input.
External memory interface write high-byte control. Takes priority over
digital I/O.
LATJ<5> data output.
PORTJ<5> data input.
External memory interface chip enable control output. Takes priority
over digital I/O.
LATJ<6> data output.
PORTJ<6> data input.
External memory interface lower byte enable control output. Takes
priority over digital I/O.
LATJ<7> data output.
PORTJ<7> data input.
External memory interface upper byte enable control output. Takes
priority over digital I/O.
LATJ4
Bit 4
RJ4
—
TRISJ3
LATJ3
Bit 3
RJ3
—
RTSECSEL1 RTSECSEL0
TRISJ2
Description
LATJ2
Bit 2
RJ2
2010 Microchip Technology Inc.
TRISJ1
LATJ1
Bit 1
RJ1
TRISJ0
LATJ0
Bit 0
RJ0
—
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