PIC18F67K22-I/PTRSL Microchip Technology, PIC18F67K22-I/PTRSL Datasheet - Page 183
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PIC18F67K22-I/PTRSL
Manufacturer Part Number
PIC18F67K22-I/PTRSL
Description
MCU PIC 128K FLASH XLP 64TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F65K22T-IPTRSL.pdf
(548 pages)
3.PIC18F65K22T-IPTRSL.pdf
(10 pages)
Specifications of PIC18F67K22-I/PTRSL
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
3862Byte
Cpu Speed
16MIPS
No. Of Timers
11
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F722-ISS PDF datasheet
- PIC18F65K22T-IPTRSL PDF datasheet #2
- PIC18F65K22T-IPTRSL PDF datasheet #3
- Current page: 183 of 548
- Download datasheet (5Mb)
12.9
PORTH is an 8-bit wide, bidirectional I/O port. The
corresponding Data Direction and Output Latch registers
are TRISH and LATH.
All pins on PORTH are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
TABLE 12-15: PORTH FUNCTIONS
2010 Microchip Technology Inc.
RH0/AN23
RH1/AN22
RH2/AN21
RH3/AN20
RH4/CCP9/
P3C/AN12/
C2INC
Legend:
Note:
Pin Name
PORTH, LATH and
TRISH Registers
PORTH is available only on the 80-pin
devices.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Function
C2INC
CCP9
AN23
AN22
AN21
AN20
AN12
RH0
RH1
RH2
RH3
RH4
P3C
Setting
TRIS
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
0
1
x
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
—
Preliminary
LATH<0> data output.
PORTH<0> data input.
A/D Input Channel 23.
Default input configuration on POR. Does not affect digital input.
LATH<1> data output.
PORTH<1> data input.
A/D Input Channel 22.
Default input configuration on POR. Does not affect digital input.
LATH<2> data output.
PORTH<2> data input.
A/D Input Channel 21.
Default input configuration on POR. Does not affect digital input.
LATH<3> data output.
PORTH<3> data input.
A/D Input Channel 20.
Default input configuration on POR. Does not affect digital input.
LATH<4> data output.
PORTH<4> data input.
CCP9 compare/PWM output. Takes priority over port data.
CCP9 capture input.
ECCP3 PWM Output C.
May be configured for tri-state during Enhanced PWM.
A/D Input Channel 12.
Default input configuration on POR. Does not affect digital input.
Comparator 2 Input C.
PIC18F87K22 FAMILY
EXAMPLE 12-8:
BANKSEL ANCON2
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL TRISH
MOVLW
MOVWF
CLRF
CLRF
0Fh
ANCON2
0Fh
ANCON1
0CFh
TRISH
PORTH
LATH
Description
; Select bank with ANCON2 register
; Configure PORTH as
; digital I/O
; Configure PORTH as
; digital I/O
; Select bank with TRISH register
; Value used to
; initialize data
; direction
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
; Initialize PORTH by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
INITIALIZING PORTH
DS39960B-page 183
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