PIC18F67K22-I/PTRSL Microchip Technology, PIC18F67K22-I/PTRSL Datasheet - Page 157
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F67K22-I/PTRSL
Manufacturer Part Number
PIC18F67K22-I/PTRSL
Description
MCU PIC 128K FLASH XLP 64TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F65K22T-IPTRSL.pdf
(548 pages)
3.PIC18F65K22T-IPTRSL.pdf
(10 pages)
Specifications of PIC18F67K22-I/PTRSL
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
3862Byte
Cpu Speed
16MIPS
No. Of Timers
11
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F722-ISS PDF datasheet
- PIC18F65K22T-IPTRSL PDF datasheet #2
- PIC18F65K22T-IPTRSL PDF datasheet #3
- Current page: 157 of 548
- Download datasheet (5Mb)
REGISTER 11-18: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
REGISTER 11-19: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
CCP10IP
TMR5GIP
R/W-1
R/W-1
(1)
CCP10IP and CCP9IP are unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
TMR5GIP: Timer5 Gate interrupt Priority bit
1 = High priority
0 = Low priority
Unimplemented: Read as ‘0’
RC2IP: EUSART Receive Priority Flag bit
1 = High priority
0 = Low priority
TX2IP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
CTMUIP: CTMU Interrupt Priority bit
1 = High priority
0 = Low priority
CCP2IP: ECCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
CCP1IP: ECCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
RTCCIP: RTCC Interrupt Priority bit
1 = High priority
0 = Low priority
CCP<10:3>IP: CCP<10:3> Interrupt Priority bit
1 = High priority
0 = Low priority
CCP9IP
R/W-1
U-0
—
(1)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
RC2IP
CCP8IP
R/W-1
R-1
CCP7IP
TX2IP
R/W-1
R-1
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F87K22 FAMILY
CTMUIP
CCP6IP
R/W-1
R/W-1
(1)
CCP5IP
CCP2IP
R/W-1
R/W-1
x = Bit is unknown
x = Bit is unknown
CCP1IP
CCP4IP
R/W-1
R/W-1
DS39960B-page 157
RTCCIP
CCP3IP
R/W-1
R/W-1
bit 0
bit 0
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