PIC18F67K22-I/PTRSL Microchip Technology, PIC18F67K22-I/PTRSL Datasheet - Page 69
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F67K22-I/PTRSL
Manufacturer Part Number
PIC18F67K22-I/PTRSL
Description
MCU PIC 128K FLASH XLP 64TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F65K22T-IPTRSL.pdf
(548 pages)
3.PIC18F65K22T-IPTRSL.pdf
(10 pages)
Specifications of PIC18F67K22-I/PTRSL
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
3862Byte
Cpu Speed
16MIPS
No. Of Timers
11
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F722-ISS PDF datasheet
- PIC18F65K22T-IPTRSL PDF datasheet #2
- PIC18F65K22T-IPTRSL PDF datasheet #3
- Current page: 69 of 548
- Download datasheet (5Mb)
TABLE 4-4:
2010 Microchip Technology Inc.
Note 1:
2:
3:
4:
5:
Power-Managed
SEC_IDLE mode
PRI_IDLE mode
RC_IDLE mode
Sleep mode
T
runs concurrently with any other required delays (see Section 4.4 “Idle Modes”).
Includes postscaler derived frequencies. On Reset, INTOSC defaults to HF-INTOSC at 8 MHz.
T
(parameter F12, Table 31-7); it is also designated as T
Execution continues during T
The clock source is dependent upon the settings of the SCS (OSCCON<1:0>), IRCF (OSCCON<6:4>)
and FOSC (CONFIG1H<3:0>) bits.
CSD
OST
Mode
(parameter 38, Table 31-12) is a required delay when waking from Sleep and all Idle modes, and
is the Oscillator Start-up Timer (parameter 32, Table 31-12). T
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
IOBST
Clock Source
MF-INTOSC
MF-INTOSC
MF-INTOSC
HF-INTOSC
HF-INTOSC
HF-INTOSC
LF-INTOSC
LF-INTOSC
LF-INTOSC
LP, XT, HS
LP, XT, HS
EC, RC
EC, RC
HSPLL
HSPLL
(parameter 39, Table 31-12), the INTOSC stabilization period.
SOSC
Preliminary
(2)
(2)
(2)
(2)
(2)
(2)
(5)
PIC18F87K22 FAMILY
PLL
.
T
Exit Delay
OST
T
T
T
T
T
T
IOBST
CSD
CSD
CSD
OST
CSD
RC
+ t
(1)
(1)
(1)
(3)
(1)
is the PLL Lock-out Timer
rc
(4)
(3)
Clock Ready
Status Bits
SOSCRUN
DS39960B-page 69
MFIOFS
HFIOFS
MFIOFS
HFIOFS
HFIOFS
MFIOFS
OSTS
OSTS
None
None
None
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