PIC18F67K22-I/PTRSL Microchip Technology, PIC18F67K22-I/PTRSL Datasheet - Page 57
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F67K22-I/PTRSL
Manufacturer Part Number
PIC18F67K22-I/PTRSL
Description
MCU PIC 128K FLASH XLP 64TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18F65K22T-IPTRSL.pdf
(548 pages)
3.PIC18F65K22T-IPTRSL.pdf
(10 pages)
Specifications of PIC18F67K22-I/PTRSL
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
3862Byte
Cpu Speed
16MIPS
No. Of Timers
11
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F722-ISS PDF datasheet
- PIC18F65K22T-IPTRSL PDF datasheet #2
- PIC18F65K22T-IPTRSL PDF datasheet #3
- Current page: 57 of 548
- Download datasheet (5Mb)
FIGURE 4-1:
FIGURE 4-2:
4.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer. In this mode, the primary clock is
shut down. When using the LF-INTOSC source, this
mode provides the best power conservation of all the
Run modes, while still executing code. It works well for
user applications which are not highly timing-sensitive
or do not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
block – either LF-INTOSC or INTOSC (MF-INTOSC or
HF-INTOSC) – there are no distinguishable differences
between the PRI_RUN and RC_RUN modes during
execution. Entering or exiting RC_RUN mode, how-
ever, causes a clock switch delay. Therefore, if the
primary clock source is the internal oscillator block,
using RC_RUN mode is not recommended.
2010 Microchip Technology Inc.
Peripheral
Note 1: Clock transition typically occurs within 2-4 T
Program
Counter
SOSCI
OSC1
Note1: T
Clock
Clock
RC_RUN MODE
CPU Clock
CPU
PLL Clock
Peripheral
Program
Counter
Output
2: Clock transition typically occurs within 2-4 T
SOSC
OSC1
Clock
Q1
OST
SCS<1:0> bits Changed
Q2
= 1024 T
PC
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q3
Q4
OSC
Q1
; T
PLL
Q1
1
= 2 ms (approx). These intervals are not shown to scale.
T
OST (1)
PC
2
Q2
Clock Transition
3
OSC
T
OSTS bit Set
Q3
PLL (1)
Preliminary
.
OSC
.
(1)
PC + 2
n-1
Q4
PIC18F87K22 FAMILY
This mode is entered by setting the SCS1 bit to ‘1’. To
maintain software compatibility with future devices, it is
recommended that the SCS0 bit also be cleared, even
though the bit is ignored. When the clock source is
switched to the INTOSC multiplexer (see Figure 4-3),
the primary oscillator is shut down and the OSTS bit is
cleared. The IRCF bits may be modified at any time to
immediately change the clock speed.
n
Q1
1
Note:
Transition
2
Clock
n-1 n
(2)
Q2
Caution should be used when modifying a
single IRCF bit. At a lower V
possible to select a higher clock speed
than is supportable by that V
device operation may result if the V
F
PC + 2
OSC
Q3
specifications are violated.
Q2
Q4
Q3 Q4
Q1
Q1
PC + 4
Q2
PC + 4
Q2
DS39960B-page 57
Q3
Q3
DD
. Improper
DD
, it is
DD
/
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